AMD answered the agentic CPU launches from Intel and NVIDIA by modeling a 100 kW CPU rack where EPYC 9965 “Turin” delivers 2.37x the NVIDIA Vera throughput baseline and roughly 1.6x Intel Xeon 6980P, with EPYC “Venice” projected at 3.30x. The harder question for buyers is whether AMD EPYC rack-scale leadership is a durable advantage or a core-density claim that benchmarks the wrong Intel part, given that Intel’s own Foxconn-built Xeon 6+ rack is planned to reach 36,864 cores.
What Is Covered in This Article:
- AMD’s blog reframes the agentic CPU debate from component benchmarks to rack-level throughput inside a fixed 100 kW, 2P envelope, treating the discrete CPU rack that runs orchestration, databases, caching, and middleware as the tier that scales with concurrent agents.
- AMD claims EPYC 9965 “Turin” delivers a 2.37x normalized geometric mean throughput over NVIDIA Vera and roughly 1.6x over Intel Xeon 6980P, with EPYC “Venice” projected to extend the Vera comparison to 3.30x.
- AMD’s “shipping density today, not proprietary promises” message targets NVIDIA’s ARM-based Vera and Intel’s Rackscale Blueprints, pitching x86 software continuity, standard liquid-cooled racks, and commercial availability.
- AMD’s rack-scale win is a core-density result that benchmarks the 128-core Xeon 6980P, not Intel’s 288-core Xeon 6+, and Intel proposes its own Foxconn-integrated CPU rack that already reaches 36,864 cores, exceeding AMD’s projected Venice density.
- AMD EPYC’s case for rack-scale leadership
The News: AMD published a blog on June 9, 2026, authored by Raghu Nambiar, Corporate Vice President of Datacenter Ecosystems and Application Engineering in the Server Business Unit, arguing that agentic AI should be evaluated at the rack level rather than through isolated component claims. Across a workload suite spanning general-purpose compute, server-side Java, web serving, key-value, in-memory caching, and relational databases, AMD reports that EPYC 9965 “Turin” (192 cores) delivers a 2.37x normalized geometric mean throughput over the NVIDIA Vera baseline (88-core “Olympus”) and roughly 1.6x over Intel Xeon 6980P “Granite Rapids-AP” (128 cores), which itself turns in 1.46x over Vera. AMD projects next-generation EPYC “Venice” (256 cores) to extend the advantage to 3.30x. All configurations are normalized to a modeled 100 kW rack on 2P platforms, with AMD positioning the density as available today on standard x86 infrastructure rather than a future architecture buyers must wait for.
Can AMD EPYC Extend its Lead Over Vera and Xeon in the Agentic Data Center?
Analyst Take: AMD didn’t make the market wait for their Advancing AI event to respond to claims made by agentic CPU competitors at Computex 2026. Intel used Computex to recast itself as a systems company and pushed the unit of competition up from the socket to the rack, claiming up to 150,000 agents per Xeon 6+ rack. NVIDIA used GTC Taipei to put the Vera CPU into full production and wrap it inside the Vera Rubin POD and the DSX platform, reframing the metric from cores per dollar to tokens per megawatt. Both moves dragged the conversation away from the chip and toward the rack and the power budget. AMD’s response accepts that framing completely, then argues that AMD EPYC rack-scale performance already wins the fight both rivals just defined, on hardware that enterprises can deploy today.
AMD Accepts the Rack-Scale Frame, Then Claims It
AMD did not relitigate whether the rack is the right unit of analysis. It conceded the point, because the discrete CPU rack is exactly where high core count cashes out. This is not the handful of host CPUs inside a GPU server. It is the standalone rack of CPU nodes that runs the orchestration, transactional, web, caching, and middleware services around an agentic deployment, the tier that scales with the number of concurrent agents rather than the size of any model, and that an enterprise stands up alongside its accelerator racks. Inside a fixed 100 kW envelope, the processor that packs the most cores per watt converts that envelope into the most aggregate service throughput. EPYC 9965 brings 192 cores against Xeon 6980P’s 128 and Vera’s 88, and AMD’s claimed 2.37x throughput over Vera and roughly 1.6x over Xeon falls almost directly out of that core arithmetic once power and nodes-per-rack are normalized. Venice at 256 cores extends the same logic to a projected 3.30x. AMD recognizes that the metric its competitors elevated is the metric AMD is built to win, and then refuses to let them own it.
The supporting density claim sharpens the point. AMD says an EPYC “Turin” deployment in a Dell PowerEdge IR7000 supports more than 27,000 cores per rack today, with Venice architected beyond 36,000 in the same rack class, against 22,500 for a Vera 88-core 2P configuration. While Intel plans to reach this density with its new server designs, AMD tests its ability to execute by arguing “the density positioned as future-looking is already being exceeded with standard infrastructure available now.”
AMD Targets Core Density for Agentic Efficiency
AMD’s rack-scale leadership is, underneath the framing, a core-density result on a workload suite chosen to reward core density. This target aligns with Intel’s case for Xeon 6+ and responds to NVIDIA’s prioritization of per-core throughput. The benchmark tasks in the blog post are highly parallel and thus the workloads where more cores win. AMD selected the infrastructure layers that surround agentic systems precisely because those tiers scale with concurrent agents rather than model size. Futurum Research reinforces the demand side directly, finding that agentic workloads are pulling CPU-to-GPU ratios back toward 1:1, with some configurations demanding up to 64 logical CPU cores per GPU (Futurum, “Can the CPU Market Meet Agentic AI Demand?,” February 2026). More cores per accelerator means a larger CPU rack tier sitting beside every GPU rack, which is exactly the build-out AMD wants to supply.
The Density Jab Has an Intel-Shaped Hole
AMD’s “not proprietary promises” line reads cleanly against NVIDIA. Vera lands at 22,500 cores in a 2P rack; it is Arm rather than x86, and it primarily arrives embedded in the vertically integrated Vera Rubin POD. Against that target, AMD’s standard x86 density story reinforces the share capture story that has driven high growth to date. Against Intel, it has a hole, and the hole is twofold. First, AMD benchmarks the 128-core Xeon 6980P “Granite Rapids-AP,” a P-core part, rather than Intel’s actual rack-density product, the 288-core Xeon 6+ built on the efficiency-core line for exactly the throughput-bound suite AMD ran. AMD picked the Intel chip that loses, not the one that contests the density crown. Second, Intel is proposing a proprietary CPU rack of its own. Through Rackscale Blueprints, integrated with Foxconn and announced at Computex, a single liquid-cooled Xeon 6+ rack reaches 36,864 cores, which Intel positions as the highest CPU density to date and as the discrete CPU tier that deploys alongside accelerator infrastructure. That figure matches and slightly exceeds AMD’s projected beyond-36,000-core Venice future, and it far exceeds the 27,000 cores Turin ships today. So the number AMD frames as its forward-looking advantage is one Intel already claims. AMD’s “shipping density, not proprietary promises” jab is sharpest against NVIDIA, but the rival that actually contests AMD on CPU-rack density is Intel.
Where AMD Actually Wins the Discrete CPU Rack
AMD’s durable edge is therefore not raw density, because Intel contests that today. It is standard-infrastructure deployability and x86 software continuity. AMD reaches 27,000-plus cores on a Dell PowerEdge IR7000 or any comparable standard liquid-cooled rack, with no new architecture, no porting, and the x86 software ecosystem enterprises already run. NVIDIA’s Vera carries Arm migration risk primarily inside a closed, fully optimized POD. Intel’s 36,864-core rack is a Foxconn-integrated Rackscale Blueprints reference design. AMD is the only one of the three offering the dense discrete CPU rack on commodity x86 racks an enterprise can stand up now, and that is the switching-cost moat. Futurum’s 1H 2026 Data Center Semiconductors Forecast shows Arm-based alternatives reaching 25.0% of data center CPU share in Q4 CY2025 against Intel’s 45.3%, in a market on pace to grow 38.8% in 2026. x86 continuity is AMD’s direct defense against the Arm incursion Vera represents.
To win the density crown outright rather than on deployability alone, AMD has to do two things. It has to confront Intel’s 288-core Xeon 6+ rack head-on instead of benchmarking the 128-core 6980P, because the current comparison invites exactly the rebuttal Intel will make. And it has to ship Venice on TSMC 2nm in the second half of 2026, moving the standard-rack ceiling past 36,000 cores so that AMD leads on density and on deployability at the same time. Layer in tokens per dollar per watt, the metric Futurum expects to dominate infrastructure decisions, and AMD has the complete argument. The most agentic service capacity per rack, on hardware you can buy today.
What to Watch:
- Whether Venice executes on TSMC 2nm in 2H 2026 and whether the projected 3.30x and beyond-36,000-core claims survive contact with shipping silicon and production liquid-cooled racks, since both figures are currently modeled estimates.
- Whether AMD confronts Intel’s 288-core Xeon 6+ rack and the Foxconn-integrated 36,864-core Rackscale Blueprints design directly.
- Adoption of Intel’s Rackscale Blueprints CPU rack and whether enterprises accept an integrated, partner-defined reference rack to reach top density or prefer AMD’s standard path.
- Arm’s structural share gain through Vera, Graviton, and the Arm AGI CPU
- Whether enterprises actually value “deploy today on standard x86” over NVIDIA’s integrated POD and Intel’s integrated rack
Read the full blog post on the AMD website.
Declaration of generative AI and AI-assisted technologies in the writing process: This content has been generated with the support of artificial intelligence technologies. Due to the fast pace of content creation and the continuous evolution of data and information, The Futurum Group and its analysts strive to ensure the accuracy and factual integrity of the information presented. However, the opinions and interpretations expressed in this content reflect those of the individual author/analyst. The Futurum Group makes no guarantees regarding the completeness, accuracy, or reliability of any information contained herein. Readers are encouraged to verify facts independently and consult relevant sources for further clarification.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
