AMD announced on October 1 that the Versal AI Core XQRVC1902 adaptive SoC is sampling with early access customers in an enhanced space-grade organic lidless package designed for missions lasting up to 15 years. AMD is testing the device to MIL-PRF-38535 Class Y, the highest reliability class for spaceflight components with flight-qualified units expected in the second half of 2027. Futurum views the move as AMD extending the same 7nm silicon from commercial new space constellations to the assurance tier where rad-hard incumbents have faced no AI-capable challenger.
What Is Covered in This Article:
- Sampling of the Versal AI Core XQRVC1902 adaptive SoC in an enhanced space-grade organic lidless package with early access customers
- Class Y qualification testing under MIL-PRF-38535, the highest reliability standard for spaceflight components, with flight-qualified units expected in 2H 2027
- Package design for 15-year missions spanning geosynchronous, cislunar, heliocentric, and deep space orbits, including human-rated programs
- Pin compatibility with commercial, defense-grade, and space-grade VC1902 devices in the 2197-ball grid array package
- Competitive mapping against Microchip RT PolarFire, Frontgrade Gaisler, NanoXplore, and the COTS orbital compute field
The News: AMD announced on October 1 that it is sampling the Versal AI Core XQRVC1902 adaptive SoC in an enhanced space-grade package with early access customers. The organic lidless package incorporates conservative design rules and an enhanced organic substrate material to mitigate thermal and mechanical stresses in space, paired with space-grade chip capacitors that have established flight heritage. AMD is testing the device to the U.S. military specification MIL-PRF-38535 Class Y, the highest level of quality and reliability under the standard for spaceflight components, and designed the package for missions lasting up to 15 years. Target applications include human-rated, long-duration, and other high-value missions across geosynchronous Earth orbit, cislunar orbit, heliocentric orbit, and deep space. The new package is pin-compatible with existing Versal AI Core VC1902 commercial, defense-grade, and space-grade devices in the 2197-ball grid array package.
“The availability of XQR Versal AI Core adaptive SoC samples in AMD advanced space-grade packaging marks an important milestone toward Class Y qualification and enables customers to construct engineering models using this technology for missions demanding absolute reliability,” said Ken O’Neill, Aerospace and Defense lead systems architect at AMD. Class Y flight-qualified units are expected in the second half of 2027.
AMD’s Class Y Versal Package Extends AI Silicon to 15 Year Space Missions
Analyst Take: This announcement moves AMD’s most capable space silicon into the one procurement tier it could not previously reach. The XQRVC1902 completed Class B qualification in November 2022, a level suited to low Earth orbit and missions of roughly 7 years and the device has since built flight heritage across the commercial new space market. Class Y is a different buyer. Human-rated programs, geosynchronous communications payloads, and deep space probes specify the highest assurance class and have historically settled for rad-hard processors a generation or more behind commercial compute. The XQRVC1902 brings 400 first-generation AI Engine tiles, dual-core Arm Cortex-A72 scalar processors, and programmable logic to that tier, a compute profile no Class Y incumbent approaches. Futurum’s report Orbital Computing Can Reach $1 Trillion Addressable Market by 2030 frames the demand side: as orbital compute scales, the share of missions that justify long-duration assurance grows with it. The sampling milestone matters because engineering model construction is when programs commit to a device and AMD just opened that window 2 years ahead of flight qualification.
Class Y Qualification Moves From Ceramic to Organic Packaging
Class Y qualification grew out of ceramic non-hermetic flip-chip packaging and the established Class Y parts in the market, including AMD’s own XQRKU060 Kintex UltraScale FPGA, qualified in ceramic formats. A 7nm adaptive SoC with 2,197 balls at 45mm x 45mm exceeds what ceramic packaging economically supports, so AMD adapted its screening and qualification flows from MIL-PRF-38535 for organic substrates when it qualified the XQRVC1902 to Class B in 2022. The new package extends that approach to the 15-year mission profile through conservative design rules, an enhanced substrate material, and capacitors with prior flight heritage, while the lidless construction improves thermal performance in vacuum, where every watt must exit through conduction and radiation.
AMD is qualifying a packaging technology as much as a device. If the organic lidless format passes Class Y, every future XQR Versal device inherits a validated path to the highest assurance tier. AMD disclosed in late 2025 that Versal RF (VR1602 and VR1652) and Versal AI Edge Gen 2 (2VE3858 and 2VE3558) space-grade devices are in qualification for Class B and Class Y, so the pipeline behind this package is already public. The risk is in the qualification itself. Class Y demands extended Group C life testing, and AMD’s own disclosures around the XQRVC1902 program referenced thousands of hours of stress data still required for flight-level signoff, which is why the 2H 2027 availability date deserves tracking rather than assumption.
Pin Compatibility Turns One Board Design Into a Mission-Class Range
The 2197-ball package is pin-compatible across commercial, defense-grade, and space-grade VC1902 devices, and that continuity is the commercial promise of the announcement. A payload developer can prototype on commercial silicon, fly a Class B device on a LEO demonstration, and move the same board design to a Class Y part for a geosynchronous or cislunar program. Development cost amortizes across mission classes, and the Vivado and Vitis toolchains, the AI Engine programming model, and the FPGA fabric design transfer without modification. This mirrors the platform economics AMD runs in terrestrial embedded markets, where one silicon family spans industrial, defense, and commercial grades. Qualification screening at Class Y compresses volume and raises unit cost by design, so the space-grade business will stay small in revenue terms against AMD’s data center segments. Its value is that space programs design a device for a decade or longer, second sources rarely displace an incumbent mid-program, and each Class Y design win anchors follow-on procurement across a mission family. The pin-compatible range also widens AMD’s funnel at the bottom. A new space startup that selects the commercial VC1902 for cost becomes a qualified lead for the XQR part the moment its constellation business pursues government or human-rated contracts.
Rad-Hard Incumbents Compete on Assurance While AMD Competes on Compute Density
The Class Y and adjacent high-assurance field has been defined by devices that prioritize radiation hardness over throughput. Microchip’s RT PolarFire RTPF500ZT reached MIL-STD-883 Class B and QML Class Q qualification with 481,000 logic elements and immunity to configuration upsets from its nonvolatile fabric, and its RT PolarFire SoC with a Linux-capable RISC-V subsystem is sampling with a roadmap to QML Class V and Class Y. Frontgrade Gaisler’s GR740 quad-core LEON4FT anchors European institutional missions, with the octa-core GR765 in development offering LEON5FT or NOEL-V RISC-V cores at 1 GHz alongside an embedded NanoXplore eFPGA. NanoXplore’s rad-hard NG-Ultra FPGAs serve European sovereignty requirements directly. Each of these vendors can argue superior radiation behavior with flash-based and rad-hard-by-design devices resist configuration upsets that SRAM-based fabrics like Versal must mitigate through scrubbing and architectural redundancy.
AMD’s counterargument is compute density. No rad-hard device fields anything comparable to 400 AI Engines optimized for the matrix operations that onboard inference, synthetic aperture radar processing, and beamforming demand, and the gap is not close. The procurement question for each program becomes whether mission processing requirements justify managing an SRAM-based device’s radiation mitigation burden in exchange for an order-of-magnitude compute advantage. For Earth observation payloads that must process sensor data into downlink-ready products onboard, compute is the top priority.
Flight Qualification Costs Eight Years of Silicon Progress
The XQRVC1902’s silicon entered commercial production in 2019, which means Class Y flight units in 2H 2027 will qualify a die design roughly 8 years old. This is the structural economics of high-assurance space silicon, and the market is bifurcating around it. The COTS path flies current commercial parts and accepts shorter missions: Google’s Project Suncatcher launched Trillium TPUs on October 1 for a 1-year LEO mission, Starcloud flew an NVIDIA H100 in November 2025, and NVIDIA announced its Space-1 Vera Rubin module at GTC 2026, a field Futurum covered in Can AMD’s Edge Silicon Scale to the Trillion Dollar Orbital Opportunity?. The assurance path accepts silicon age in exchange for 15-year reliability, because a Europa-bound probe or a crewed vehicle cannot reboot its way out of a failure. AMD is the only vendor fielding credible products on both paths with one architecture, from commercial off-the-shelf devices for new space through Class B constellation parts to this Class Y package.
The bear case is that the bifurcation widens faster than AMD qualifies new devices. If COTS orbital compute proves 5-year missions viable with current-generation silicon, as Google’s radiation data suggests it may for LEO, the addressable share of the high-assurance tier compresses toward the genuinely irreplaceable missions, a market measured in hundreds of units per year. The bull case is that cislunar infrastructure, Artemis-era programs, and proliferated GEO architectures expand exactly the mission classes Class Y serves, with flight-qualified availability in 2H 2027 timed to those payload build cycles.
What to Watch:
- Whether AMD discloses named early access customers or program wins in human-rated or deep space missions
- Whether Versal AI Edge Gen 2 and Versal RF space-grade devices reach Class B or Class Y qualification milestones in 2027
- Whether Microchip advances RT PolarFire SoC from engineering samples toward its stated QML Class V and Class Y roadmap
- Whether COTS orbital compute missions demonstrate multi-year reliability that narrows the assurance premium Class Y commands
Read the complete announcement on the AMD newsroom.
Sources
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
