Cadence announced that its Tensilica IP group and Analog Devices jointly developed the SHARC-FX core inside ADI’s new ADSP-SC84x/2184x automotive audio processors, claiming 5X the performance of the prior SHARC+ generation on a move from 28nm to 16nm. The design retires one of the industry’s longest-running proprietary DSP architectures in favor of licensed IP tuned for on-chip AI inference.
What is Covered in this Article
- Cadence and ADI co-development of the SHARC-FX core inside the ADSP-SC84x/2184x automotive audio family
- A claimed 5X performance gain over the SC59x SHARC+ generation on a 28nm-to-16nm process transition
- On-chip AI inference through optimized NN kernels for LiteRT alongside deterministic real-time audio
- The end of ADI’s in-house SHARC instruction set after three decades of proprietary DSP design
- Competitive stakes versus Qualcomm cockpit SoCs and other Tensilica licensees
The News: Cadence announced that its Tensilica IP Group and Analog Devices, Inc. (ADI) jointly developed the SHARC-FX processor core at the center of ADI’s next-generation ADSP-SC84x/2184x automotive audio platform. The new family succeeds the ADSP-SC59x/2159x line, moves from 28nm to 16nm process technology, and adds an LPDDR4 memory interface, expanded on-chip L2 memory, a dedicated hardware security module, and two optional connectivity cores with mainline Linux support. Cadence and ADI claim the SHARC-FX core delivers 5x the performance of the previous-generation SHARC+ core through an enhanced VLIW SIMD architecture, an expanded instruction set, and higher operating frequency, with optimized neural network kernels for frameworks such as Google’s LiteRT, enabling AI audio workloads to run on the DSP rather than the host CPU.
ADI SHARC-FX Runs on Cadence IP: Is the Proprietary DSP Era Over?
Analyst Take: The ADI SHARC-FX closes out one of the longest runs of proprietary processor architecture in the semiconductor industry. ADI introduced the original SHARC, the Super Harvard Architecture Single-Chip Computer, in 1994 and has evolved the instruction set in-house through the SHARC+ cores that power the ADSP-SC59x family in premium vehicle audio systems today. The ADSP-SC84x/2184x generation replaces that lineage with a core built on Cadence’s Tensilica technology platform, the same foundation behind Tensilica DSPs for audio, vision, and radar. ADI frames the change as a performance decision, and the claimed 5x uplift over SHARC+ is material if it is validated in production silicon. The deeper story is that AI workloads have changed the economics of owning an instruction set. A proprietary ISA now obligates its owner to build and maintain neural network kernel libraries, compiler infrastructure, and framework integrations that IP licensors amortize across dozens of customers. ADI concluded that the differentiation lives elsewhere.
Licensed IP Ends 32 Years of In-House DSP Design
SHARC earned its longevity. The architecture scaled from 400 to 2,000 SHARC+ MIPS across the ADSP-2156x and SC59x generations and built an installed base across automotive, professional, and consumer audio that runs decades of hand-tuned signal-processing code. ADI previewed the transition earlier with the ADSP-2183x/SC83x series, the first SHARC-FX parts, which run at up to 1 GHz, issue up to four instructions per cycle, execute eight float32 multiply-accumulate operations per cycle on 256-bit vectors, and deliver more than 3.5x the DSP performance of the ADSP-2156x while remaining pin-compatible with predecessors. The SC84x family now carries that architecture into ADI’s flagship automotive sockets at 16nm.
The Tensilica platform ADI adopted was built for exactly this arrangement. Tensilica was founded in 1997 on the premise that tuning a processor to a specific problem yields order-of-magnitude gains in performance and energy efficiency, and its Tensilica Instruction Extension (TIE) technology generates the RTL, compiler support, and instruction set simulator for custom instructions from a single source description. Andrew Lanfear, head of Automotive Audio & Networking at ADI, said the ability to create custom instructions using TIE “allows us to accelerate proprietary audio and voice algorithms while providing dedicated DSP resources for real-time voice offload.” The implication is that ADI keeps its algorithmic secret sauce in hardware while outsourcing the architecture, toolchain, and AI software stack underneath it.
AI Inference Economics Forced the Architecture Decision
Automotive audio workloads are migrating from hand-designed filters to pre-trained models. Road noise cancellation, personal sound zones, music source separation, and real-time vocal removal increasingly run as neural network inference, and Cadence states the SHARC-FX instruction set was expanded specifically to execute these models alongside conventional DSP kernels. Supporting that shift on a proprietary ISA would require ADI to port and optimize every major edge AI framework alone. Cadence spreads that cost across its licensee base, and buyers are responding: Futurum’s coverage of Cadence’s Q2 FY 2026 earnings found IP revenue growing more than 40% YoY within total revenue of $1.58 billion, a record $8.1 billion backlog, and a first Tensilica DSP win at STMicroelectronics. ADI is the second major analog incumbent in a year to license the franchise rather than extend an internal architecture, and Cadence introduced the Tensilica HiFi iQ DSP for voice AI in January 2026 to press the same advantage.
The move fits ADI’s automotive posture. Futurum’s analysis of ADI’s Q3 FY 2026 earnings recorded automotive revenue of $998.2 million, up 16% YoY on content gains in ADAS, infotainment, and electric powertrains within a first-ever $4.02 billion quarter. Premium audio content per vehicle is one of the few infotainment categories where ADI sets the reference architecture, through the ADSP processors, the A2B bus, and the SigmaStudio+ and CrossCore toolchains that DSP Concepts’ Audio Weaver framework plugs into. Protecting that franchise through the software-defined vehicle transition justifies swallowing architectural pride.
Deterministic Offload Must Outrun Cockpit Centralization
The bear case is structural. Software-defined vehicle architectures concentrate compute into central cockpit SoCs, and Qualcomm’s Snapdragon platforms bundle Hexagon DSP capacity that automakers may deem good enough for audio, while NXP and Texas Instruments field their own cockpit and audio silicon. ADI’s counterargument is determinism. Amol Borkar, group director of product management for Tensilica DSPs at Cadence, said the SHARC-FX runs AI audio workloads efficiently “while the host CPU remains dedicated to vehicle-domain and operating system functions.” That framing aligns with Futurum’s broader view that heterogeneous, purpose-built silicon is displacing general-purpose consolidation wherever latency and power budgets are constrained. Real-time acoustic processing at seat-level granularity is a poor fit for a shared, virtualized SoC.
Two risks deserve flagging. The 5x performance claim is vendor-supplied and awaits independent testing in production vehicles. And the architecture ADI now builds on is available to rivals. Cadence licenses the same technology platform broadly, so ADI’s moat narrows to its TIE custom instructions, its A2B ecosystem, and three decades of automotive audio relationships rather than an instruction set no competitor could touch. That is likely still a defensible position, yet it has changed quickly with a shifting AI landscape.
Read the complete announcement of the joint DSP development on the Cadence website.
What to Watch
- Whether ADSP-SC84x design wins appear in 2028-2029 model-year software-defined vehicle platforms
- Whether independent benchmarks validate the vendor-claimed 5x uplift over SHARC+
- Whether SHARC+ code migration friction slows the installed base’s move to SHARC-FX
- Whether Qualcomm and NXP absorb premium audio processing into central cockpit SoCs
- Whether Cadence converts additional analog incumbents to Tensilica licenses following STMicroelectronics and ADI
Sources
1. Cadence Tensilica IP Powers Analog Devices’ Next-Generation DSP Architecture, Cadence, September 2026
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
Olivier Blanchard is Research Director, Intelligent Devices. He covers edge semiconductors and intelligent AI-capable devices for Futurum. In addition to having co-authored several books about digital transformation and AI with Futurum Group CEO Daniel Newman, Blanchard brings considerable experience demystifying new and emerging technologies, advising clients on how best to future-proof their organizations, and helping maximize the positive impacts of technology disruption while mitigating their potentially negative effects. Follow his extended analysis on X and LinkedIn.
