Cadence Pushes ChipStack to Level 5 Verification Autonomy While Synopsys Extends AgentEngineer Into Multi-Physics
What Is Covered in This Article:
- Cadence extended the ChipStack AI Super Agent to Level-5 autonomy at NVIDIA GTC Taipei, running on NVIDIA Nemotron models and OpenShell, with NVIDIA citing more than 40x faster RTL validation.
- Synopsys countered with breadth, demonstrating an Ansys IcePak thermal agent for GPU cooling inside NVIDIA NemoClaw at Computex.
- Synopsys moved agentic multi-physics forward, extending autonomous workflows from code-like front-end tasks into thermal and physical closure, the part of the flow where respins originate.
- Cadence and Synopsys agree on the real moat: tight tool integration and token-efficient structured data, rather than the model, which favors the EDA incumbents over the frontier labs.
The News: At Computex 2026, during NVIDIA GTC Taipei, the agentic EDA race between Cadence and Synopsys came into sharper focus. Cadence extended its ChipStack AI Super Agent to Level-5 autonomy and positioned it as the industry’s first fully autonomous virtual design engineer, built on its EDA portfolio, running on NVIDIA Nemotron models, and secured by the NVIDIA OpenShell runtime. In the workflow highlighted in NVIDIA’s keynote, OpenAI Codex orchestrates ChipStack as it drives Cadence Xcelium simulation and Jasper formal verification, and NVIDIA reports more than 40x faster RTL validation, cutting a typical five-week loop to under a day.
Synopsys advanced a different front. Building on the L4 AgentEngineer design and verification workflow and Multiphysics Fusion technology it introduced at Synopsys Converge in March, Synopsys demonstrated an autonomous AI engineer that uses Ansys IcePak to mesh, simulate, and optimize GPU cooling inside NVIDIA NemoClaw on the Computex show floor. Thomas Andersen, Vice President of AI and Machine Learning at Synopsys, used his Computex forum keynote to frame the direction as engineers defining intent while agents orchestrate execution across the full design flow.
Cadence and Synopsys Accelerate Agentic EDA Race at Computex
Analyst Take: The agentic EDA race accelerated across two divergent bets on what autonomous chip design means. Cadence is racing toward depth in verification autonomy. Synopsys is racing toward breadth across the full flow, and it pushed the frontier into agentic multi-physics. The Agentic EDA concept was validated by Jensen Huang as one of the best examples of Useful AI, incorporating the latest reasoning models with deterministic software.
Cadence Gains NVIDIA’s Acclaim in Verification Autonomy
ChipStack’s jump to Level-5 and the 40x RTL validation figure are real signals, and verification is the right beachhead. Spec-to-RTL and verification are the tasks closest to software development, where agentic coding already works. NVIDIA’s endorsement, including Jensen Huang’s line about hiring hundreds of thousands of Cadence super agents, gives the depth play a powerful reference customer. ChipStack is front-end and verification-centric, and Cadence’s analog and back-end agents, ViraStack and InnoStack, are not generally available until later this year. Depth in one domain leaves a lengthy roadmap to end-to-end autonomy,
Synopsys Breaks Ground in Multi-Physics Breadth
Synopsys’s counter is that it showed both front-end and back-end agentic workflows at its Converge conference in March, then moved agentic multi-physics forward at Computex. The IcePak thermal agent for GPU cooling extends autonomy into the hardest and least automated part of the flow. Multiphysics Fusion, which folds Ansys thermal, voltage drop, and electromagnetic engines into the implementation tools, lets teams measure physical effects accurately enough to cut the margins they would otherwise guardband into the design. An agent then runs optimization loops on top of that higher-accuracy analysis. This is the expansion of the end-to-end vision. Front-end agents generate RTL, but thermal and physical closure is where respins originate, especially in 3DIC, and that is the domain Synopsys is now automating. Cadence does not have an Ansys-equivalent multi-physics stack, which is the structural gap behind this divergence.
The Deepening Moat for EDA Vendors Over Frontier Coding Agents
For their competition, Cadence and Synopsys describe the same moat over frontier AI. A coding agent pointed at raw EDA tools can read log files and write skill scripts, but it produces lower-quality, less repeatable results and burns far more tokens. The EDA advantage is tight tool integration, special machine interfaces, and structured data that feed the right context to each model call. Agent count becomes a competitive metric, which echoes the agents-per-rack metric now governing the data center. The conclusion from both camps is that the defensible layer is the grounded tool chain and the orchestration, not the model, which is why the EDA incumbents, rather than the frontier labs, are positioned to own autonomous chip design. The reasoning model advances of the past year made the agents viable, but they did not commoditize the toolmaker.
Diverse Adopters and Better Models Compound the Upside
The commercial opportunity scales with two variables. The first is what the early adopters do next. Cadence names MediaTek, NVIDIA, Altera, Qualcomm, and Tenstorrent among its first ChipStack users. If those teams push agents beyond front-end verification into analog, 3DIC, and the collaborative, multi-vendor chiplet packages that increasingly define advanced designs, the addressable work for agentic EDA expands far past where it started. Diversity of design type and collaboration across vendors both multiply the number of agent-addressable tasks per project.
The second variable is model improvement. Nemotron 3 Ultra, NVIDIA’s 550-billion-parameter mixture-of-experts model, claims roughly 5X faster inference and about 30 percent lower cost than leading open models, and each step like it lowers the token cost that gates continuous agent use while raising the autonomy a vendor can credibly offer. More design domains, more cross-vendor collaboration, and cheaper, stronger reasoning models turn agentic EDA from a verification accelerator into a consumption-based growth market, and the incumbent that owns the grounded tools captures most of it.
Where Hardware Engineers Will Push Back
Hardware engineers we speak with will treat industry-first and autonomy-level claims as marketing first before verification. Cadence’s Level-5 and Synopsys’s L4 are self-graded labels on scales that are not standardized across vendors, so they are not directly comparable. Both companies are showcasing pieces of a flow rather than a fully tied-together end-to-end system, and named customer references and audited metrics remain thin on both sides. There is also a bottleneck neither marketing slide highlights. Once agents automate the human analysis loop, the runtime of the underlying EDA tools becomes the limiting factor, which is why GPU acceleration of simulation, implementation, and signoff is the quiet variable that will decide who actually delivers speed at scale.
What to Watch:
- How Cadence answers Synopsys’s Ansys-backed multi-physics stack, and how quickly its analog and back-end agents, ViraStack and InnoStack, reach general availability.
- Whether the industry converges on a shared L1 to L5 scale or each vendor keeps self-grading
- The GPU acceleration roadmaps both vendors are building with NVIDIA, since runtime, not agent intelligence, will gate end-to-end speed
- Named references and repeatable, audited metrics rather than vendor-cited multipliers, on both verification and multi-physics closure
- Whether structured-API token efficiency holds as the durable differentiator if frontier labs try to ground general agents directly in EDA flows
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
