The Futurum Group at Marvell’s Industry Analyst Day 2023 with Sandeep Bharathi – Futurum Tech Webcast

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Transcript:

Ron Westfall: Hello everyone. I’m Ron Westfall of The Futurum Group and you’re joining us here today at the Marvell Industry Analyst Event. And I’m very pleased to have a distinguished guest with us today, Sandeep Bharathi. And to start things off, first of all, Sandeep, please share who you are and what you do at the Marvell.

Sandeep Bharathi: Yeah, thank you Ron. It’s great to be here and to share with you about what exciting things we are doing at Marvell. I’m the Chief Development Officer here at Marvell. I joined Marvell in February of 2019, so it’s going to be soon five years. And I lead the development and central engineering activities. And what that really means is really developing all the foundational technologies that our business units and the products use. And that’s very pivotal for all the target and markets that we address.

Ron Westfall: Excellent. Thank you Sandeep for that intro. And so, hey, let’s dive right in. The hot topic of the year is AI and the impact that it’s having on the semiconductor industry as well as portfolio development. And from your perspective, what is it about AI that’s driving portfolio innovation? What’s making all of the difference here in our ecosystem?

Sandeep Bharathi: Yeah, excellent question. I think AI really, a lot of people talk about training, inference, these large language models and many of the technical jargon that we have known since ChatGPT came online. But really the technology depends upon all the compute infrastructure. And when we say the compute infrastructure, people focus more on the compute, but there’s also the data that gets generated and the data has to move from one place to the other, whether it is within the chip or between chip to chip or even off chip and board. And that’s the data boom and challenge. And the more the data gets generated, the more the data moves. And AI is all about bringing data from one place to other securely, computing it and storing it and which is our mission statement, right? So no matter whether it’s AI today, yesterday, or in the future, these challenges will still remain and that’s what we are intent on solving.

Ron Westfall: Yes, it’s very exciting times and I think one thing that people are very interested in hearing about is, for example, AI’s impact on Moore’s law. And first of all, can you explain what is Moore’s law and from your view, what is going to be different about Moore’s law as AI unfolds?

Sandeep Bharathi: Yeah, great question. I think Moore’s law, as you know, is not a physical law. It was an observation by Dr. Gordon Moore in the sixties when he published and he saw the trend that computing power doubles at the rate of 18 months to two years. And over the period of the last four or five decades, that has been right. And now as we move to the limits of semiconductor scaling, which means every process geometry by classical scaling meant that if you were say, let’s go back to 28 nanometer going to 20 or 16 nanometer, you could pack in two times the number of transistors in a given square millimeter or a DAI. But as we have gone to 5 nanometer, 3 nanometer and 2 nanometer in advanced CMOS, it’s slowing down, it’s still there. People go to advanced technologies for three reasons. One is to pack more transistors in a given piece of silicon. The other one is higher performance for the silicon that you pack in. And the third is energy efficiency or the lower power. Those are the three reasons. But because the limits of physics are almost being reached, there are newer innovations for transistors. So we had Planar transistors that went to FinFET. Now there are what they call the Gate-all-around transistors or nano sheets and it’ll soon be some other material. But you also have to integrate a number of these silicon chips into 3D stacking to advance the scaling in a way or to keep the Moore’s Law alive as well as packaging strategies of 2 1/2D, 3D stacking, with the Chip-on-Wafer-on-Substrate activities. Those are aspects, that is what AI also is bringing it up to how much more can we pack and how much more can we get in and out of the package.

Ron Westfall: Yes, no, I agree. I think packaging is going to be a huge differentiator for how silicon is selected. And I think that is an excellent historical overview of Moore’s Law and what is going on today. Forward-looking Moore, what is Marvell doing to first of all take advantage of these capabilities and also specifically in relation to IP networking capabilities?

Sandeep Bharathi: A very good point to segue into is I want to move from what we talk about compute in AI to really the data movement. So advanced technologies allow us to actually give the power efficiency low energy for data movement. But what is also happening is the analog mix signal characteristics or the scaling, for example, the caches of the SRAM or the SerDes or the serializer/deserializer architectures. They’re not scaling as effectively as digital circuits. So what we need to do is really increase the bandwidth through different signaling mechanisms. One way I will, just to explain is if you have a 10 lane highway, you can only send so many cars at a time with so many passengers. But one way to double the number of passengers is, for example, go from two-seater passenger car to an SUV which seats six or a double-decker bus, which would probably seat 50 passengers.

Likewise, we figured out how to send the bits and bytes by using the technology to cram in more transistors, but also evolve innovations in signaling transitions so we can send more bits or gigabits per second. That’s another metric that we use in order to widen the bandwidth capability with also the highest energy efficiency or low power. And that is done by a lot of innovations in analog mix signal circuitry as well as you need different algorithms for error correction because when they go a certain distance, just like they lose the fidelity and we need to build in through DSP algorithms. And that’s what is very evident with our optical DSPs and coherent DSPs, which are various different signaling, which is PAMM four and optical and QPSK and qualm signaling in our coherent. So that’s how we take advantage of not only the advances in semiconductors, but also innovations in signaling techniques, innovations in our analog mix signal portfolio.

Ron Westfall: Yeah, I can understand that. And I think that does lay the foundation for the drilling down more on a specific aspect of the portfolio that I see increasingly becoming important, and that is the connectivity IP capabilities. Naturally, I know folks out there are very keen to know more about what Marvell’s doing in that area specifically, and also any insight as to the direction that you’re seeing these capabilities going.

Sandeep Bharathi: Yeah. Let me step back a bit on the connectivity IP portfolio that we build. I talked to you about the one important figure of merit that we all care about is the gigabits per second per millimeter. Per millimeter of how much you need to travel within the chip or across the chip. And the energy efficiency metric is called picojoules per bit, how much energy that you expend by transferring a bit. So if we go back, there was the classic NRZ or non-return to zero where your signaling is zero and one. Then we went to PAM four, and PAM four is basically you use four levels to transfer bits and with coherent it’s really 16 different levels. And so PAM four went from 56 to 112, and now we are at 224. And what is very critical in all these is how effectively your modulation schemes are used in really the signaling board rate or the bandwidth and how much correction that we can overlay on top of the signal loss that is there when you traverse across chips. Innovations are happening on a regular basis. So we were the PAM four signaling with our NFI acquisition with 112 gig then we are now at 224 gig. We recently announced the very first 1.6 terra optical DSP called Nova, and on the coherent side we introduced Orion, which is our first 800 gig coherent DSP. And all this is proof in what we are able to do. It’s not showing any signs of slowdown because the need for AI means more compute, more bandwidth and innovations will continue. I’m confident that we are approaching this in a manner first principles and crazy enough to try it.

Ron Westfall: Oh, sure. No, I think it’s just that we’re seeing the innovation engine moving forward. It’s built in and so that makes for a great foundation for more innovation. And so yeah, this could be an opportunity to drill down on some of the applications that are benefiting from this. That includes, for example, data center interconnectivity and what else are you seeing in terms of the application side that’s really benefiting from these breakthroughs?

Sandeep Bharathi: Yeah, let me draw your attention to what you’re holding in your hand.

Ron Westfall: Product placement. Perfect.

Sandeep Bharathi: Yes. What you’re seeing is really our very first 51 terra switch, and you can look at that size of the package. The DAI has 512 lanes of 112 gig circuits, which is packed all in that piece of silicon. We were talking about this earlier in our conversation that packaging and thermal and power management is such an important vital piece. It’s not always the bits and bytes. It’s not always we’ll go from seven nanometer to fine nanometer to whatever is the next process technology of choice. It is really a holistic design process of chip package interaction, package thermal interaction, thermal and power management, and how all this is brought together in innovative substrates and connectors and what we call thermal interface materials to manage the thermal performance between where the DAI is and the organic package is. So all this is really, there’s innovations on just every vector that makes that DAI and that entire package. So with these hyperscalers and data centers, the challenges are you have a pizza box or you have a module, optical module, everything has a power envelope and you don’t have a product or we don’t have a product if we don’t meet those specifications. And that’s where the innovations are just not on the connectivity or IP portfolio, just not the process technology, it’s just the entire platform. So that becomes very imperative as we are addressing products for the hyperscalers.

Ron Westfall: Yeah, I am certainly impressed by this packaging. You can grip it in the palm of your hand and so what’s not to, and I think that definitely sets us up Sandeep for the next topic that people are very interested in and that is what Marvell is investing in. Can you provide us some not only portfolio development direction but also a teaser on what’s going to happen in terms of, for example, marketing initiatives in that area?

Sandeep Bharathi: So I think the investment is in several different areas. For example, standards are becoming an important piece so you can go at it alone. So we are in several consortiums that takes investment, that needs to know where the puck is headed. That’s one area of investment. The other area is for example, from a foundry technology perspective, what other things are out there. For TSMC and the rest of the foundries are looking at various ways to get power, meaning there’s talk about backside power and how does it help the integrity of, so we are looking at these advanced things that are three, five years out. Now we have heard of 224, the next frontier is 448, right? And what does 448 mean in terms of signaling standards, modulation schemes. And then it’s also EDA tools, for example, what AI techniques we should use in order for our chips to be better, faster, cheaper, lower power. So what worked yesterday, it’s the famous Einstein score or maybe attributed to Einstein, is you can’t solve tomorrow’s problems with yesterday’s solutions. So we have to be continuous in, how do we build the chips? Are we doing it right? Do we need to build models such that we help our design team, a very capable design team to take AI algorithms into account such that there is less bugs? Because a bug is very expensive when found after the fact, right? And if you’re not first to market, you basically lost the plot. So AI will change how we are going to build the chips too. So there is investment in terms of what techniques that we need to use in our development process. So again, there is different vectors of investment in advanced technologies to build silicon software. How do we integrate all these things together and work with the ecosystem partners? Because we are not going at it alone. We have a hybrid strategy. We will develop stuff that we are good at, but we are also depending upon the ecosystem to get other aspects that our hyperscalers and our customers need.

Ron Westfall: Yeah, I agree wholeheartedly. In fact, that was my next question that you addressed it superbly. And that is what about the partnerships earlier today we talked about Nvidia, ARM and F5 came up. In terms of partnerships, what do you see Marvell doing in terms of strengthening that aspect of the Marvell proposition?

Sandeep Bharathi: So in our analyst day, you heard from many of my colleagues talk about our flexible business model for building customized silicon. Therein, our partnerships are with our customers and with our vendors because there are many different kinds of products that we will build, right? Sometimes, for example, let’s take a look at chiplets, right? If you need to integrate chiplets, that requires a different business model. It could be our own, it could be something from a third party. And thereby the ecosystem partnerships come into play, both in terms of our foundry partners, our customers and customers who will have to get HPM chiplets from somebody else and EDA IP providers. Sometimes the ecosystem will mean that we may have to do modeling a little bit differently. So that’s how we are proceeding. We take each engagement as an engagement that is very customized.

Ron Westfall: I see that as part of the strategic vision and basically bringing it together in terms of Marvell’s process capabilities, IP connectivity, and naturally packaging proposition. How is Marvell going to continue driving innovation across the ecosystem? Quite simply make a difference with the partners and the customers out there?

Sandeep Bharathi: So you’ve heard about what we are doing with silicon photonics. These are long lead time items that we continuously put out test vehicles. Sometimes we learn from them to further the technology portfolio. These are between one to three years, three to five years. We have to experiment because sometimes it may not be successful and sometimes you learn with the mistakes that we do and thereby gets stronger at what works and what doesn’t work. So these are the various aspects by which we are looking at future technologies. Some we can talk about and some we can’t.

Ron Westfall: Thank you so much, Sandeep.

Sandeep Bharathi: Thank you.

Ron Westfall: And with that, thank you everyone for joining the Futurum Tech Webcast. Please be sure to join our website to be able to see our latest installment. And with that, have a good semiconductor day everyone.