Analyst(s): Brendan Burke
Publication Date: May 13, 2026
SiFive has launched the Performance P570 and P550 Gen 3, its third-generation out-of-order RISC-V processor cores delivering significant vector performance improvements and full RVA23 profile compliance for consumer and edge applications. The announcement signals a direct architectural challenge to Arm’s midrange portfolio by bringing fully out-of-order scalar and vector execution to power-constrained device segments where such capabilities have historically been absent.
What is Covered in This Article:
- SiFive’s third-generation Performance P570 and P550 core announcement
- Fully out-of-order vector execution in a power-efficient consumer-class core
- RVA23 profile compliance and its role in RISC-V software ecosystem maturation
- Competitive positioning against Arm’s stagnant midrange core portfolio
- Dot product extensions enabling up to 21x vectorized workload gains
The News: SiFive announced its Performance P570 Gen 3 and P550 Gen 3 processor cores, the company’s third-generation out-of-order RISC-V application processors designed for consumer devices, edge AI endpoints, and embedded control applications. The P570 includes a 128-bit RISC-V vector pipeline with new dot product extensions, while the P550 delivers the same architectural improvements without vector capabilities. Both cores implement the full mandatory and most optional extensions of the recently ratified RVA23 instruction set architecture profile.
The 13-stage pipeline, three-wide-issue cores have already been delivered to lead customers, with silicon tape-outs expected in the second half of 2026. SiFive states the P570 Gen 3 delivers 2x to 21x improvements on vectorized subtests compared to the first-generation P550, while reducing power consumption versus prior generations. The cores support systems of up to 16 coherent cores, vector cryptography extensions, BFloat16 data types, and control flow integrity security features, including landing pads and shadow stacks.
SiFive’s P570 Gen 3 Tests Whether RISC-V Can Challenge Arm in Consumer Silicon
SiFive’s P570 Gen 3 Tests Whether RISC-V Can Challenge Arm in Consumer Silicon
Analyst Take: SiFive’s P570 Gen 3 represents an inflection point for RISC-V in application processor markets that Arm has dominated without meaningful competition for over a decade. The announcement makes an architectural statement that fully out-of-order scalar and vector execution can be delivered within the power and area budgets that consumer and edge devices demand. Combined with comprehensive RVA23 compliance, SiFive is positioning this core as the vehicle through which RISC-V becomes a credible alternative for mainstream Linux and Android devices, not merely embedded controllers. The timing aligns with SiFive’s recent $400 million Series G raise, providing the capital to sustain a prolonged competitive campaign against Arm’s entrenched ecosystem.
Fully Out-of-Order Vector Execution Redefines Midrange Core Economics
The P570 Gen 3’s most architecturally significant attribute is its fully out-of-order execution across both scalar and vector pipelines, a rare characteristic at this power and area class. In conventional designs, vector units operate in order even when paired with out-of-order scalar engines, creating throughput bottlenecks when workloads interleave scalar and vector instructions. SiFive achieves parallel out-of-order execution through shared resources that avoid the area expansion typically associated with such designs in data center processors. This approach enables the core to sustain high vector throughput without degrading scalar performance, addressing a fundamental tension in mixed-workload processing. The architectural choice is particularly relevant as edge AI inference workloads increasingly demand both strong general-purpose performance and sustained vector compute within tight power envelopes. The implication is that SiFive has found a microarchitectural path to deliver data-center-class execution characteristics at consumer-device power budgets, a combination that Arm’s current midrange portfolio does not offer.
RVA23 Compliance Converts Architectural Capability Into Ecosystem Access
The P570 Gen 3’s comprehensive RVA23 implementation transforms what could be an isolated performance story into a platform play with software ecosystem consequences. RVA23 has become the gating requirement for major software stacks: Linux distributions target it as their baseline, Google mandates it for Android. By implementing not only all mandatory extensions but most optional ones, SiFive positions the P570 Gen 3 as the most comprehensive RVA23 deployment available, positioning it as a preferred development target for software teams building RISC-V support. NVIDIA and Red Hat used SiFive’s existing P550 board for porting RISC-V to CUDA and enterprise Linux porting efforts, respectively, indicating the likely impact of this implementation.
Software compatibility has historically been RISC-V’s weakest competitive dimension against Arm, where decades of ecosystem investment create substantial switching costs. The breadth of implementation also future-proofs customer designs against potential software requirements that may later promote optional extensions to mandatory status. RVA23 compliance has become a market access credential, and SiFive has secured the most complete version of it.
Arm’s Midrange Vacuum Creates an Asymmetric Competitive Window
SiFive identifies Arm’s Cortex-A75 and Cortex-A76 cores, delivered approximately a decade ago, as the closest competitive comparison to the P570 Gen 3 in terms of market positioning. Arm has concentrated its recent innovation on premium mobile cores such as the Cortex-X series and infrastructure-class Neoverse designs, leaving the efficient midrange segment without a meaningful architectural refresh. This creates an asymmetric opportunity for SiFive where the P570 Gen 3 competes not against Arm’s best current technology but against aging designs that lack vector extensions, modern security features, and the efficiency gains of a decade of process and microarchitectural advancement. Customers designing digital TVs, wearables, IoT endpoints, and embedded controllers have been forced to use cores whose architecture predates the current AI workload environment. SiFive’s ability to deliver vectors, dot product acceleration, and out-of-order execution in this segment represents genuine differentiation rather than parity. Arm’s strategic neglect of this tier has created a window that RISC-V vendors can exploit before any competitive response materializes.
Dot Product Extensions Signal SiFive’s Standards-First Commercialization Model
The dot product extensions included in the P570 Gen 3 deliver up to 21x performance improvements on vectorized workloads such as object detection, yet add negligible die area. SiFive developed these extensions and subsequently donated them to RISC-V International for standardization, consistent with the company’s historical pattern of pioneering capabilities and then open-sourcing them to strengthen the broader ecosystem. This approach serves a dual commercial purpose: it establishes SiFive as the first-mover implementor while simultaneously growing the addressable market by ensuring software toolchains and libraries optimize for extensions that become industry standard. The strategy contrasts with proprietary extension approaches that fragment the software ecosystem and create vendor lock-in. For customers evaluating RISC-V IP vendors, SiFive’s standards-first model reduces the risk that custom extensions will become orphaned or incompatible with future software developments. SiFive’s donation strategy is a calculated mechanism to convert technical leadership into ecosystem-wide adoption that reinforces its commercial position.
What to Watch:
- Whether lead customer tape-outs in the second half of 2026 translate into publicly named design wins that validate consumer market traction
- How quickly developer boards featuring the P570 Gen 3 reach the market to accelerate software ecosystem readiness beyond the existing P550-based HiFive Premier
- Whether Arm responds with a midrange core refresh that closes the architectural gap SiFive has identified in the efficient out-of-order segment
- How the P570 Gen 3 pairs with SiFive’s Intelligence family cores in practice for integrated edge AI system-on-chip designs
- Whether competing RISC-V IP vendors such as Andes Technology narrow the implementation gap with their own RVA23-compliant third-generation cores
See the full press release on SiFive’s Performance P570 Gen 3 announcement on the company website.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
