NVIDIA contributed its Vera Rubin rack and compute tray designs to the Open Compute Project at the 2026 OCP Global Summit, announced the Vera CPU is shipping in MGX rack form, and disclosed that Meta is adopting Spectrum-6 for its Vera Rubin AI factories. NVIDIA also brought Google Falcon Transport to its networking roadmap and defined the USFP 400Gb/s-per-lane optical module with Cisco. Futurum’s read is that NVIDIA is unbundling its AI factory into openly manufacturable layers so the industry’s supply base tools up around NVIDIA’s geometry.
What Is Covered in This Article:
- Vera Rubin rack and compute tray designs contributed to OCP through the MGX 1.2 specification
- The Vera CPU shipping now in MGX form, with ASRock Rack’s dual-Vera 2U already in the ODM catalog
- Meta adopting NVIDIA Spectrum-6 as its first 102.4 Tb/s Ethernet switch ASIC
- Google Falcon Transport support coming to ConnectX-10 SuperNICs and BlueField DPUs
- The NVIDIA and Cisco USFP pluggable optics form factor for 400Gb/s-per-lane fabrics
- Competitive implications for AMD Helion, Intel, Arm, and the Ethernet switching field
The News: NVIDIA (NASDAQ: NVDA) announced on October 12 at the Open Compute Project (OCP) Global Summit in San Jose that it has contributed its Vera Rubin rack and compute tray designs to OCP through the third-generation MGX architecture. The updated MGX 1.2 specification spans compute racks, CPU racks, storage, and networking, and adds rack-scale blind-mate liquid cooling, a liquid-cooled 5,000A busbar, and rack deployments up to 250kW.
NVIDIA said the Vera CPU is shipping now in multiple form factors on the same MGX architecture, positioned as the first CPU purpose-built for agentic AI; ASRock Rack is showing a dual-Vera 2U for agentic pipelines at the summit. Meta is adopting NVIDIA Spectrum-6, a 102.4 Tb/s Ethernet switch ASIC with 128 ports of 800GbE, for the networks connecting its Vera Rubin deployments, running Meta’s open-source FBOSS network operating system on its N-IceCube switch. NVIDIA and Google announced Falcon Transport support on future ConnectX-10 SuperNICs with a roadmap extending to BlueField DPUs, and NVIDIA and Cisco introduced the Ultra-Dense Small Form Factor Pluggable (USFP), the first optical module designed for 400Gb/s-per-lane signals, with TE Connectivity and Amphenol building the hardware ecosystem.
“Building the world’s largest AI factories starts with rethinking the smallest of connections,” said Gilad Shainer, Senior Vice President at NVIDIA.
NVIDIA also launched four open-source DSX OS software components — Config Manager, Cluster Readiness Engine, Rack Management Service, and Cluster API Provider — and joined AMD, Google, and Meta to publish the Open Data Center Specification v0.7.
NVIDIA Unbundles the AI Factory and Turns Openness Into Its Strong Suit
Analyst Take: NVIDIA opened Vera Rubin to OCP because the binding constraint on its growth is no longer silicon but manufacturing throughput for AI factories. When a specification is open, equipment makers can begin fabricating against it immediately instead of waiting for proprietary designs to settle with individual customers, and the MGX ecosystem at this year’s summit has nearly 100 partners, more than double last year’s 40. The implication is that NVIDIA is unbundling the AI factory into openly manufacturable layers — racks, trays, busbars, switch software interfaces, and now optics — publishing each while it still defines the frontier so the industry’s entire supply base tools up around NVIDIA’s geometry. With 85.1% of enterprise AI compute decision makers actively using or evaluating NVIDIA, the company is converting dominant mindshare into structural dependency through standards leadership.
The Vera CPU Is Already a Catalog Item in the ODM Tier
Vera shipping in a dedicated CPU rack formalizes the division of labor Futurum has tracked all year, with Vera Rubin NVL72 handling training and inference while a separate CPU tier absorbs the orchestration, code execution, tool calling, and sandboxing around every model call. The claims rest on refreshed benchmarks: 2x gains over Grace on agentic workloads measured in part on SPEC 2026 and 1.8x on Terminal-Bench, which runs real agent tasks in real containers, with Meta reporting 2x on DCPerf and Redpanda 3.5x on Apache Kafka.
The ecosystem is moving faster than the benchmarks. ASRock Rack’s 2UXGM-VERA2 turns the 256-CPU MGX rack NVIDIA sells hyperscalers into a 2U increment an enterprise can buy one at a time, joining the dual-Vera systems Supermicro and HPE revealed earlier this year, so standalone Vera has reached the challenger-ODM price tier within seven months of its GTC debut. AMD answered with Helion racks of up to 32,768 EPYC “Venice” cores, and Intel’s Xeon 6+ targets the identical tier. Merchant architectures now compete with no neutral benchmark regime, which makes SPEC 2026 adoption a battleground in its own right.
Meta on Spectrum-6 Is the Strongest Ethernet Win NVIDIA Has Posted
Meta adopting Spectrum-6 as its first 102.4 Tb/s switch ASIC is the week’s most commercially consequential disclosure. Meta built its switching identity on Broadcom merchant silicon and its own FBOSS software, so a Spectrum-6 win inside Meta’s IcePack rack places NVIDIA silicon at the heart of the hyperscaler most committed to vendor-independent networking, sold into an open software stack running on the Switch Abstraction Interface NVIDIA helped standardize.
NVIDIA’s counter to the commoditization question is Spectrum-X Multiplane, which spreads GPU traffic across up to eight network planes and reroutes around hardware failures in under three milliseconds, a claimed 30x advantage over software approaches because detection happens in SuperNIC hardware. Falcon Transport extends the pattern to Google, implementing its reliable transport protocol on ConnectX-10 and BlueField. The entanglement now spans switching and transport. The risk runs the other way, since every integration that runs NVIDIA silicon under hyperscaler software reduces NVIDIA’s control, and Broadcom’s Tomahawk roadmap will contest every socket.
USFP Positions Pluggables as the Volume Alternative to Co-Packaged Optics
The Cisco partnership bets that pluggable optics can make the 400Gb/s-per-lane transition many assumed would force co-packaged optics. USFP packs 16 full-duplex lanes in an OSFP-sized footprint with a path to 32 lanes and 12.8 Tb/s per module, delivering 4x the bandwidth density and approximately 1.3x the power efficiency of 200Gb/s-per-lane optics, per the companies’ figures, on a new two-step insertion connector supporting up to 100W of module power without embedded cooling.
Futurum has argued the 1.6TbE transition will reshape data center architecture from the ground up, and USFP is the scale-out answer, preserving the field-serviceable deployment model operators trust while NVIDIA reserves co-packaged optics for where power density forces it. The multi-source structure with TE Connectivity, Amphenol, and an MSA promised in the coming months resembles an industry standard rather than a two-vendor lock-in. The deciding variable is whether 400G-per-lane electrical signaling proves manufacturable at transceiver volumes before CPO economics improve.
Software Stickiness Closes the Loop
Hardware openness alone does not create durable competitive advantage. NVIDIA’s launch of four open-source DSX OS components — Config Manager, Cluster Readiness Engine, Rack Management Service, and Cluster API Provider — addresses the operational layer where switching costs accumulate. This matters because 50% of decision makers cite a stronger software ecosystem and easier portability as the top factor that would make them consider switching AI accelerator vendors.
By open-sourcing software derived from DGX Cloud operations, NVIDIA simultaneously lowers deployment friction for new adopters and deepens familiarity with its operational toolchain. The participation in the Open Data Center Specification v0.7 alongside AMD, Google, and Meta, and the OCP Grid Resilience Specification requiring near-full load restoration within two seconds of grid disturbances, further embeds NVIDIA’s operational assumptions into industry-wide standards.
What to Watch:
- Whether ODM and OEM Vera Rubin derivative racks reach production in the first half of 2027
- Whether independent benchmarks validate Vera’s 2x agentic claims against EPYC Venice and Xeon 6+
- Whether standalone Vera demand materializes beyond CoreWeave and Meta into enterprise order books
- Whether Meta extends Spectrum-6 beyond initial Vera Rubin clusters or dual-sources with Broadcom Tomahawk 6
- Whether the USFP MSA lands in the coming months with members beyond the founding four
Read more details on the NVIDIA website.
Sources
- OCP Global Summit: Amid Ecosystem Adoption, NVIDIA Opens Vera Rubin Architecture to Help Scale AI Factories Worldwide, Nvidia, October 2026
Declaration of generative AI and AI-assisted technologies in the writing process: This content has been generated with the support of artificial intelligence technologies. Due to the fast pace of content creation and the continuous evolution of data and information, The Futurum Group and its analysts strive to ensure the accuracy and factual integrity of the information presented. However, the opinions and interpretations expressed in this content reflect those of the individual author/analyst. The Futurum Group makes no guarantees regarding the completeness, accuracy, or reliability of any information contained herein. Readers are encouraged to verify facts independently and consult relevant sources for further clarification.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.
Read the full Futurum Group Disclosure.
Other Insights From Futurum:
NVIDIA Wants Agent Safety Enforced in Silicon
The $246 Billion CPU Opportunity’s Winning Chip Has Not Been Designed Yet
VAST DataEnclave Unifies Proprietary Models and Sensitive Enterprise Data
Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
