Analyst(s): Brendan Burke
Publication Date: August 5, 2026
At FMS 2026, Marvell announced additions to its AI memory infrastructure portfolio spanning SSD controllers, CXL memory expansion and pooling, and optical shared memory. The launches target the KV cache bottleneck in agentic AI inference and signal that CXL is moving from hyperscaler evaluation into deployment.
What Is Covered in This Article:
- Marvell’s FMS 2026 announcement expands its AI memory infrastructure portfolio across the Bravera SC6 PCIe 6.0 SSD controller, Structera CXL memory expansion and pooling, and Photonic Fabric optical shared memory.
- The Bravera SC6 doubles the performance of the PCIe 5.0 Bravera SC5, supports NAND from multiple suppliers, and is expected to begin sampling in Q4 2026.
- Marvell-reported Structera benchmarks include up to 4.8x higher inference throughput and an 82.7% reduction in time-to-first-token in GPU memory-pooling configurations.
The News: Marvell Technology announced new products across its AI memory infrastructure portfolio at FMS 2026 on August 4, positioning the lineup around three tiers: server-level AI storage with the Bravera SC6 PCIe 6.0 SSD controller, rack-level CXL memory expansion and pooling with the Structera family, and pod-level optical shared memory with Photonic Fabric memory modules, NICs, and chiplets. The company frames the portfolio as a response to growing KV cache demands in agentic AI inference, where memory capacity and bandwidth increasingly gate GPU utilization and token output.
The Bravera SC6 controller supports PCIe Gen 6 and NVMe 2.2, doubles the performance of the widely deployed Bravera SC5, and runs NAND from multiple suppliers at up to 3,600 MT/s across 16 channels. It integrates 15 embedded Arm cores, including 12 Cortex-R82 cores, and is expected to begin sampling in Q4 2026. Photonic Fabric creates a shared memory tier across XPUs and racks up to 50 meters apart, enabling up to 32TB of warm KV cache offload and, per Marvell, 2 to 3x higher token throughput within existing power envelopes.
“As AI scales, memory must scale more independently of compute so resources can be deployed where they deliver the greatest value,” said Will Chu, Executive Vice President and General Manager, Custom Cloud Solutions, at Marvell. Companion blogs detail the Structera CXL portfolio: Structera X expanders shipping to hyperscalers, the Structera A 2504 near-memory accelerator with 16 Arm Neoverse V2 cores, and the Structera S 30260 CXL 3.x switch connecting 16 or 32 hosts to as much as 48TB of pooled memory.
Marvell Scales AI Memory Infrastructure to 48TB Behind a Single CXL Switch
Analyst Take: Futurum’s recent silicon coverage has tracked a single structural shift: inference is now the dominant workload, and it is memory-bound. Marvell’s FMS 2026 portfolio is the most complete silicon expression of that thesis to date. The company is betting that AI memory infrastructure becomes a distinct procurement category with its own controllers, switches, and optical tiers, and that the vendor spanning all of them wins disproportionate content per rack.
Hyperscaler Demand Moves CXL From Evaluation Into Deployment
Marvell states that Structera X 2404 and 2504 platforms are already shipping to hyperscalers, marking what the company describes as CXL adoption “moving from evaluation into real-world deployment across hyperscale environments.”
The product design reflects a specific economic proposition. The DDR4-based Structera X 2404 lets operators repurpose existing DDR4 inventory behind current-generation servers, converting stranded memory into usable CXL-attached capacity at a fraction of the cost of provisioning new DDR5. The DDR5-based 2504 targets new builds where higher bandwidth justifies the DIMM cost. Both variants front 4 DDR channels per controller and attach via standard CXL interfaces, allowing rack architects to mix expansion capacity without changing the host CPU or platform firmware.
Marvell reports up to 4.8x higher inference throughput and an 82.7% reduction in time-to-first-token in GPU memory pooling configurations using Structera. These are vendor-published benchmarks; no hyperscaler is named and no deployment volume is quantified, so production-scale validation remains pending.
Attach Economics Could Make AI Memory Infrastructure a Volume Silicon Category
The controller math is what elevates this from a niche protocol story. Each Structera X controller fronts 4 DDR channels: the DDR5-based 2504 supports 8 DIMMs per controller, while the DDR4-based 2404 reaches 12 DIMMs at three DIMMs per channel. Card capacity is configuration dependent: a lean 4-DIMM build supplies roughly 512GB, requiring 2 cards per terabyte of expansion, while a fully populated 2504 with 128GB RDIMMs approaches 1TB on a single card.
Per-socket demand is climbing toward those numbers. Trillion-parameter-class models with long context windows push working sets toward multiple terabytes per CPU. At an 8TB per-socket memory footprint, a single server could support 8 to 16 CXL expansion controllers depending on DIMM density. That estimate is Futurum’s, derived from Marvell’s published channel and DIMM configurations, and should be treated as an upper bound pending real deployment data.
The implication is that CXL controllers may start to resemble NICs a decade ago: a per-server attach category whose unit volumes scale with server shipments. Futurum projects the data center CPU market will reach $76.6 billion by 2029, growing 34.9%, and every CXL expander attaches to a CPU socket. Agentic workloads that restore the CPU to the center of AI infrastructure pull memory expansion silicon along with them.
The rest of the Structera line deepens the attach story. The Structera A 2504 accelerator pairs 16 Arm Neoverse V2 cores at 3.2 GHz with up to 4TB of capacity and 200 GB/s of bandwidth for near-memory workloads such as DLRM and vector search, and the Structera S 30260 switch connects 16 or 32 hosts to 48TB of shared memory at 4TB/s aggregate bandwidth with under 460ns round-trip latency.
Portfolio Breadth Meets Entrenched GPU-Attached Memory and a Crowded Field
The competitive field is forming quickly. Astera Labs sells Leo CXL memory controllers into the same hyperscaler accounts, XConn ships CXL switches that compete with Structera S, and Montage Technology ships CXL memory expander controllers; Samsung, SK hynix, and Micron ship CXL memory modules while serving as Marvell qualification partners. Structera interoperability is validated on Intel Xeon, AMD EPYC, and Arm platforms, which keeps Marvell neutral across the CPU vendors.
The incumbent counter-move is architectural. NVIDIA keeps KV cache inside the NVLink domain, on HBM and Grace-attached LPDDR, and its rack-scale designs leave little PCIe real estate for third-party memory tiers; Photonic Fabric is Marvell’s answer at the pod level, though its 32TB shared tier must prove itself against NVIDIA’s tightly integrated memory hierarchy. The Bravera SC6 faces a friendlier path with its NAND-agnostic architecture aligning with hyperscaler sourcing strategy, and Q4 2026 sampling positions production SSDs for the PCIe Gen 6 server platforms arriving in 2027.
Marvell holds the broadest AI memory infrastructure portfolio in the market, and breadth is a real advantage when hyperscalers want one qualified architecture instead of stitched-together point products. The risk is that CXL software maturity, the latency gap versus local DRAM, and hyperscalers’ appetite for designing their own silicon could each compress the window before this category consolidates. Watch whether deployment disclosures catch up to the portfolio ambition.
What to Watch:
- Public disclosure of a volume Structera X deployment within the next two quarters will validate the “evaluation to deployment” claim
- Bravera SC6 sampling on schedule in Q4 2026 and NAND qualifications across at least three suppliers are the signals that the hyperscale sourcing flexibility pitch is landing
- NVIDIA’s treatment of KV cache offload in its next rack-scale platforms, plus CXL 3.x product announcements from Astera Labs and XConn, will determine whether pooled memory becomes an open category or gets absorbed into proprietary GPU domains.
See the full press release on the Marvell website.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.
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Marvell’s XConn Buy Yields a Two-Pronged Open Fabric Play Against NVLink
Featured Image: Marvell
Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
