SiFive and AMD demonstrated ROCm 10.0 running Gemma 4 E2B inference on the BigSky Datacenter Development Platform at the AI Infra Summit, with P870-D CPUs as the head node and Radeon AI PRO R9700 GPUs on offload. Futurum examines what the demo proves about RISC-V head node readiness and where Instinct-scale validation still waits.
What Is Covered in This Article:
- An AMD ROCm 10.0 demonstration on the SiFive BigSky Datacenter Development Platform at the AI Infra Summit 2026
- Gemma-4-E2B inference with SiFive Performance P870-D CPUs as the head node and AMD Radeon AI PRO R9700 GPUs driving offload
- A continuing joint evaluation of ROCm optimization on RISC-V servers targeting larger models and more acceleration use cases
- BigSky SF-2U870 hardware including 32 P870-D cores at 2.0 GHz, 256GB DDR5-5600, and 64 lanes of PCIe Gen5
- ROCm arriving on BigSky three weeks after CUDA head node duty at the platform’s launch
The News: SiFive and AMD showcased a demonstration of AMD ROCm running on SiFive’s BigSky Datacenter Development Platform on September 15 at the AI Infra Summit in Santa Clara. The demonstration-only system ran the Gemma 4 E2B LLM on ROCm 10.0, with SiFive Performance P870-D CPUs acting as the head node and AMD Radeon AI PRO R9700 GPUs driving the inference offload. The two companies said they will continue to evaluate ROCm optimization on RISC-V powered servers, aiming to speed up processing times and enable more acceleration use cases and larger models.
“By combining the leading open standard architecture with their open-source software, we are enabling hyperscalers and developers to run advanced AI workloads seamlessly on RISC-V,” said Matt Langman, SVP, Datacenter at SiFive.
“This demonstration with SiFive is an early step in enabling developers to explore ROCm-based AI acceleration on RISC-V host platforms,” said Ramine Roane, corporate vice president, AI software product management, AMD. The BigSky SF-2U870 underneath the demo is built for software porting, workload tuning, and validation testing, with 32 P870-D cores at 2.0 GHz, 256GB of DDR5-5600 memory, four PCIe Gen5 x16 slots totaling 64 lanes plus PCIe Gen3 x4, two 7.68TB U.2 NVMe SSDs, and a 10/25Gb OCP 3.0 NIC.
SiFive Demos AMD ROCm on RISC-V. Is BigSky Now the Neutral Head Node?
Analyst Take: The ROCm demonstration converts BigSky’s launch thesis into evidence. Futurum viewed SiFive’s SF-2U870 in August as a porting vehicle whose real product is time, a server built to compress the software phase of hyperscaler custom SoC programs. The fastest available validation of that view is third-party software arriving on the platform, and it is arriving on schedule. CUDA ran as an LLM head node on launch day. ROCm 10.0 followed within three weeks. A development server supporting GPU software ecosystems near launch lowers the risk premium a hyperscaler assigns to a RISC-V head node in its next custom SoC program. The demo itself is modest by design. Gemma-4-E2B is a compact model, the R9700 is a workstation card, and both companies label the system demonstration-only. A second GPU software stack on RISC-V hosts moves the architecture’s data center case from a single-vendor dependency toward an ecosystem norm.
Both GPU Software Ecosystems Reached BigSky Within Three Weeks of Launch
SiFive is an IP licensor spending margin on a server, and that investment pays only when porting work on BigSky converts into licensed custom SoCs. Software gravity decides the conversion rate. At launch the platform offered RVA23 compliance, out-of-the-box Ubuntu 26.04 LTS and RHEL 10 support, and CUDA running head node duty for NVIDIA GPUs. ROCm completes the pairing that matters most for a neutral development host, because a hyperscaler evaluating RISC-V for its next custom SoC now finds both dominant GPU stacks bootable on the same 2U box. AMD prepared the ground for this port over the past year. ROCm 10 ships through TheRock, a common multi-architecture build system, and a downstream community effort at ISCAS had already ported ROCm 6.4.2 to commercial RISC-V platforms including the 64-core SG2044, with the Fedora 42 distro of Linux shipping the port. The AI Infra Summit demo pulls that community trajectory into an official AMD collaboration with the RISC-V vendor best positioned to commercialize it.
A Workstation GPU and a Compact Model Keep Instinct-Scale Validation Ahead
The demo sets expectations for scaling. The Radeon AI PRO R9700 is a $1,299 workstation card built on the RDNA 4 Navi 48 die. Gemma-4-E2B is a compact model sized for exactly this class of hardware. Data center head node economics pertain more to Instinct MI-series baseboards where eight GPUs share a chassis with an x86 EPYC host, ECC-validated memory paths, and Infinity Fabric coherency. None of that has been shown on a RISC-V host, and Roane’s “early step” framing signals AMD knows the distance.
Two structural questions shape the road from here. The first is coherent attach. NVIDIA has committed NVLink Fusion integration to future SiFive platforms, giving RISC-V hosts a path into its scale-up fabric, and AMD has announced no equivalent for RISC-V, leaving PCIe Gen5 as the available interface on BigSky. The second is channel conflict. Every Instinct system AMD sells today ships beside an EPYC socket, so an aggressive RISC-V host push would compete with AMD’s own server CPU franchise. The ROCm-on-Arm history offers the sober precedent, since official host support trailed community demand there by years even without an internal CPU rivalry in the way. The bull case is that AMD can let open source do the work, accepting community ports through TheRock and formalizing support only when customer pull justifies it, which prices the option at nearly zero.
The Demo Strengthens SiFive’s Neutrality as the Qualification Race Accelerates
Mapped against the field, the announcement’s clearest beneficiary is SiFive’s position as the neutral porting host. NVIDIA moved first, with CUDA on BigSky at launch, an investment in SiFive’s $400 million Series G, and, per the Hot Chips 2026 RISC-V tutorial, three RVA23 CPUs running in its labs versus zero a year earlier. AMD’s arrival means BigSky is the one enterprise-grade RISC-V server both GPU vendors now touch, which is precisely the asset a development platform wants to be.
The RISC-V CPU field around SiFive is crowding fast. Qualcomm’s Dragonfly roadmap pairs its Oryon-based C1000 CPUs with the Ventana Micro team acquired in December, and Tenstorrent ships Ascalon-based systems into inference. Against Arm the gap remains wide, since Grace and Vera hosts arrive with NVLink coherency, mature distribution support, and shipping volume, and against x86 the EPYC and Xeon incumbency defines the default.
BigSky’s lead customers, spanning hyperscaler, software, and major SoC hardware companies, remain unnamed, so the design-win ledger stays empty even as the software ledger fills. The competitive question worth tracking is whether GPU vendors treat RISC-V host enablement as a strategic program or a marketing checkbox. NVIDIA’s lab inventory and fabric commitment read as the former. AMD’s demonstration reads as an inexpensive probe, and the follow-through, an Instinct pairing or an official host support line in ROCm release notes, would change that outlook.
What to Watch:
- Whether ROCm adds official RISC-V host support in a numbered release
- Whether AMD demonstrates Instinct GPUs behind a P870-D head node
- Whether the ISCAS ROCm RISC-V port merges upstream through TheRock
- Whether BigSky lead customers convert into named custom SoC design wins
- Whether NVLink Fusion on SiFive platforms reaches silicon before AMD announces a coherent attach path for RISC-V hosts
Read the complete details about the demonstration here.
Sources
- **SiFive and AMD Collaborate to Optimize AMD ROCm on RISC-V Datacenter Servers**, Businesswire, September 2026
Declaration of generative AI and AI-assisted technologies in the writing process: This content has been generated with the support of artificial intelligence technologies. Due to the fast pace of content creation and the continuous evolution of data and information, The Futurum Group and its analysts strive to ensure the accuracy and factual integrity of the information presented. However, the opinions and interpretations expressed in this content reflect those of the individual author/analyst. The Futurum Group makes no guarantees regarding the completeness, accuracy, or reliability of any information contained herein. Readers are encouraged to verify facts independently and consult relevant sources for further clarification.
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
