What Is Covered in This Article:
- Intel GPU D-series specs and sampling status
- Xeon ORv3 agentic rack designs above 46,000 cores per rack
- The Intel AI for Enterprise Agent Toolkit and prompt routing economics
- Diamond Rapids preview and the five-phase agentic CPU argument
- Silicon photonics and disaggregated prefill-decode system roadmap
The News: Intel (NASDAQ: INTC) announced on October 12 at the Open Compute Project (OCP) Global Summit in San Jose new technical details for the Intel GPU D-series, formerly code-named Crescent Island, its purpose-built AI inference GPU. Built on the Xe3P architecture, the card delivers 1.3 petaflops of FP8 compute within a 350-watt, air-cooled PCIe form factor and supports up to 480 GB of LPDDR5X memory at 1.5 TB/s of bandwidth, enough to serve models up to 300 billion parameters on a single card and more than 1 trillion parameters in an 8-GPU system, per Intel’s figures. The Intel-branded card carries 160 GB, with ODM partners able to configure up to 480 GB. Customer sampling is underway, and Intel showed first silicon alongside a liquid-cooled OAM prototype that packs two GPUs per module, eight modules per standard 5U chassis.
Intel also introduced Xeon-based agentic rack designs with ecosystem partners, many on the OCP Open Rack v3 standard, with select Xeon 6+ configurations exceeding 46,000 cores per rack at 133.45 kW. The Intel AI for Enterprise Agent Toolkit, which uses Xeon to classify prompts, route requests, and orchestrate resources across heterogeneous compute, is available on GitHub today, and Intel announced Day 0 support for Meta’s Muse Glimmer model on both D-series and Xeon.
“Open models are expanding the options enterprises have for deploying AI,” said Nicolas Dubé, Corporate Vice President, Data Center Systems and Solutions Group at Intel, whose keynote framed the goal as putting every prompt in its place.
Intel D-Series GPUs Make HBM Optional for Agentic Inference
Analyst Take: The Intel GPU D-series is the first Intel data center GPU designed around what the inference market is becoming instead of what the training market was. Dubé, who joined Intel from HPE’s HPC systems organization earlier this year, argued the next phase of AI rewards right-sized intelligence placed where it serves workloads best, across clouds, enterprise IT, and the edge. The design choices follow that thesis with LPDDR5X instead of HBM to maximize capacity per dollar and per watt, a 350W air-cooled PCIe envelope that drops into existing data centers, and open software downloadable from GitHub today.
Futurum projects inference-focused accelerators will grow from roughly half of CY2025 accelerator spending to 73% by CY2030, with Agent and Reasoning-first inference alone reaching $546.0 billion, 45% of a $1.2 trillion data center semiconductor market, per Futurum’s 1H 2026 Data Center Semiconductors Market Sizing & Five-Year Forecast. Intel’s OCP showing is the most complete articulation yet of a strategy aimed squarely at that demand with a deliberately modest GPU. Cautions remain that the part is still in bring-up, general availability and pricing are undisclosed, and Intel’s accelerator track record after Ponte Vecchio and Gaudi obliges skepticism until production systems ship.
D-Series Leverages Sparse Models’ Decoupling of Capacity From Bandwidth
The D-Series architecture disclosed at Hot Chips 2026 shows Intel optimizing for memory capacity per dollar where competitors optimize for bandwidth. Intel’s analysis of published model configurations found that from Llama 2 70B to Kimi K2 1T, the bytes a server must house grew 7.5x while the bytes read per token fell 4.4x, with every sparse mixture-of-experts model reading just 3 GB to 78 GB per token regardless of total size. Capacity and bandwidth have decoupled, and Crescent Island picks capacity. At 1.5 TB/s it delivers roughly one-fifth the memory bandwidth of AMD’s HBM3E-based Instinct MI355X, yet its 480 GB ODM ceiling exceeds the MI355X’s 288 GB, and LPDDR5X costs a fraction of HBM per gigabyte.
Intel pairs the capacity bet with a compute answer for decode, arguing speculative decoding converts bandwidth-bound token generation into a compute problem, retiring 2.9 to 4.9 tokens per verification pass on frontier MoE models per LMSYS SpecBundle data, which is why the silicon is billed as prefill-optimized with high FLOP/W. The D-Series’ Xe3P core supplies the muscle through a 16-deep systolic array, 4x deeper than Xe2’s, FP8 and FP4 with microscaling (MX) format support, a doubled 1 MB register file per Xe core for deep kernel fusion, and a 32 MB unified L2 placed mid-die as a bandwidth filter that keeps 256 XMX engines fed.
The closest architectural analog is Qualcomm’s AI200, a rack-scale inference accelerator carrying 768 GB of LPDDR per card into sampling in 2026. NVIDIA validated the LPDDR-class inference concept with Rubin CPX, then reportedly pulled it from the 2026 roadmap, leaving the cost-optimized memory tier contested by challengers. Intel contests the LPDDR class with an open PCIe form factor and a Day 0 software stack of vLLM, SGLang, llm-d, and NVIDIA’s Dynamo.
Enterprise Survey Data Confirms the Direction of the Open Model Signal, Not Its Magnitude
Dubé’s most provocative data point came from outside Intel. Tokens routed to open models through the Vercel AI gateway grew from 30% of volume at the beginning of July to 78% by the end of September. Futurum’s Open-Weight AI Models drill-down survey bounds that claim for the enterprise. In the September 2026 wave, 41.5% of organizations were running open-weight models in production (n=200), up from 31.0% in July (n=100), yet among production users only 24.1% put more than half of today’s AI token usage on open-weight models, rising to 33.7% expected within 12 months (n=83). The same survey finds 53.0% of production users describing the shift as partial substitution from proprietary models, with 7.2% reporting outright substitution. The reconciliation is that the Vercel gateway measures developer traffic, where open models already dominate, while enterprise token mix is moving the same direction two steps behind.
Both signals support Intel’s routing thesis, since open models are what enterprises can place on fit-for-purpose silicon in sovereign and on-premises environments. Intel cited research showing that routing tasks across heterogeneous models can cut inference costs by 60%. The Enterprise Agent Toolkit operationalizes this by using Xeon as the classifier and router in front of whatever accelerator mix an operator deploys. The hybrid mix competes on system economics rather than peak FLOPs.
Intel Clocks 60% to 70% of an Agent Turn Off the GPU, Restoring Xeon to the Center
Intel’s OCP Expo session decomposed a single agent turn by share of wall-clock time, and the model call, prefill plus decode on the GPU, takes just 30% to 40% of it. The remaining 60% to 70% is CPU work: tool execution spanning retrieval, vector search, and RAG at 30% to 35%, data services and scheduling at 10% to 25%, state movement across KV cache, TLS, and tiering at 8%, and orchestration of sandboxes, code, and SQL at 7%, per Intel’s session figures. Each segment wants different silicon, with serialized orchestration favoring per-thread speed from high-frequency P-cores, parallel tool execution favoring core density from E-cores such as the 288-core Xeon 6+, and data services rewarding memory performance and offload engines. Intel’s conclusion on the slide was that no single “best” core serves every agentic task, so flexibility and balance of CPU capabilities decide the socket.
The proof points are that AMX acceleration runs 4x more semantic router sessions per Xeon, a Qwen model served on-premises on Xeon beats cloud API economics by more than 25% with 5% to 7% lower network latency, and memory compression through the Intel In-Memory Analytics Accelerator (IAA) recovers roughly 33% of capacity under Linux zswap.
The demand curve the whole rack strategy rides on is the projection that today’s roughly 30 million operational AI agents grow beyond 2 billion by 2030. Diamond Rapids, due in 2027 on Intel 18A-P, extends the pitch with 256 P-cores per socket, more than 1 GB of last-level cache, 16 memory channels delivering up to 1.6 TB/s, and confidential computing through TDX with post-quantum cryptography. The competitive field is crowded at exactly this tier: NVIDIA’s Vera ships now with claimed 2x agentic gains, AMD’s Helion racks scale EPYC “Venice” past 32,000 cores, and Intel’s “concurrent agents per rack at target latency” metric is a sensible frame that no neutral benchmark yet measures. The stakes justify the fight, since Futurum projects the agentic era will create a $246 billion CPU opportunity, and Futurum’s market sizing has Intel defending 45.3% of Q4 CY2025 data center CPU revenue against AMD at 29.7% and an Arm-based cohort at 25.0% that is the fastest-growing line in the build.
Photonics and Disaggregation Sketch the Road Back to Systems Relevance
The forward-looking portions of Dubé’s keynote matter as much as the products. Intel is pursuing prefill-decode disaggregated architectures that pair D-Series racks for prefill with SambaNova SN50 RDU racks for decode, a public embrace of heterogeneous third-party silicon that would have been unthinkable from Intel five years ago. Dubé also committed, on stage, to silicon photonics deployment within the next couple of years, citing Intel’s position as the only high-volume 300mm fab with integrated indium phosphide lasers and a reliability record that enables serviceable system designs, with an energy target below the long-sought 5 picojoules per bit. If delivered, optical interconnect that blends scale-up and scale-out domains becomes the substrate for runtime-orchestrated pools of CPUs, GPUs, and memory. That is a 2028-and-beyond story, and Intel’s photonics commercialization history warrants patience, but it is the first coherent systems narrative Intel has offered since exiting the supercomputing-prime business.
What to Watch:
- Whether Crescent Island reaches general availability in 2027 with competitive serving benchmarks against MI355X and Qualcomm AI200
- Whether the Vercel open-model token share trend holds across other gateways and hyperscaler-reported mix
- Whether the Enterprise Agent Toolkit gains adoption beyond Intel reference platforms
- Whether Diamond Rapids ships in 2027 with the disclosed core counts and memory throughput
- Whether silicon photonics moves from keynote commitment to a named product milestone
The announcements are detailed in the Intel OCP Global Summit newsroom post on the Intel website.
Sources
Declaration of generative AI and AI-assisted technologies in the writing process: This content has been generated with the support of artificial intelligence technologies. Due to the fast pace of content creation and the continuous evolution of data and information, The Futurum Group and its analysts strive to ensure the accuracy and factual integrity of the information presented. However, the opinions and interpretations expressed in this content reflect those of the individual author/analyst. The Futurum Group makes no guarantees regarding the completeness, accuracy, or reliability of any information contained herein. Readers are encouraged to verify facts independently and consult relevant sources for further clarification.
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
