Analyst(s): Richard Gordon
Publication Date: February 28, 2025
With its 1Q FY 2025 earnings report, Synopsys demonstrated that strong design activity remained a cornerstone of the company’s performance, driven by its leadership in hardware-assisted verification (HAV) solutions, advancements in EDA software, AI-driven innovations, and Design IP solutions. Synopsys is well-positioned to continue its growth trajectory, with key technology advancements and a strong customer pipeline contributing to ongoing success.
What is Covered in this Article:
- Synopsys 1Q FY 2025 financial results
- Hardware-Assisted Verification Leadership
- EDA Software and 2nm Projects
- AI Innovations Driving Productivity Gains
- Design IP and Key Wins
The News: For the first quarter of fiscal year 2025, Synopsys reported revenue of $1.455 billion, compared to $1.511 billion for the first quarter of fiscal year 2024. Total GAAP costs and expenses were $1.20 billion, while total non-GAAP costs and expenses were $924 million, resulting in a non-GAAP operating margin of 36.5%. GAAP earnings per share were $1.89, and non-GAAP earnings per share were $3.03.
“In Q1, Synopsys’ relentless focus on execution and innovation was evident across the business. We launched industry-leading silicon IP and hardware-assisted verification solutions while expanding generative AI capabilities in EDA,” said Sassine Ghazi, president and CEO of Synopsys. “We are continuing to see strong design activity at advanced nodes, fueled by the AI-driven reinvention of compute. As the pace and complexity of technology innovation increases, new silicon-to-systems design paradigms are essential, and Synopsys is well-positioned to deliver.”
Business Segment Results
Synopsys operates two primary business segments: Design Automation, which accounts for approximately 70% of revenue, and Design IP, accounting for the remaining approximately 30%.
- Design Automation Business Segment
- The Design Automation segment encompasses advanced silicon design tools, verification products, and related services. Revenue for this segment was $1.02 billion, up 4% Y-o-Y, as broad-based strength was partially offset by one less week in Q1’25 compared to Q1’24. Design Automation’s adjusted operating margin was 39.7%.
- Design IP Business Segment
- The Design IP segment includes embedded processors, interface IP, and security solutions. Revenue for this segment was $435.1 million, down 17% Y-o-Y, due to timing and a tough comparison with record-setting prior year. Design IP adjusted operating margin was 29.1%.
Focus on Execution as Synopsys Reports Solid 1Q FY 2025 Financial Results
Analyst Take: Synopsys’ Q1 FY 2025 performance highlights the company’s continued leadership in hardware-assisted verification, EDA software, and Design IP. Strong adoption of its advanced tools, particularly for 2nm projects and AI-driven innovations, positions Synopsys for another year of growth. As AI-driven capabilities continue to enhance the design process, Synopsys is poised to unlock even greater productivity gains, further cementing its position as a market leader in semiconductor and electronic design automation solutions.
Hardware-Assisted Verification Leadership
Synopsys strengthened its position as a leader in hardware-assisted verification (HAV) with the expansion of its HAV portfolio. The introduction of the new HAPS-200 prototyping systems and ZeBu-200 emulation systems marked a significant leap forward, delivering up to twice the performance of their previous generations. This improvement positions Synopsys at the forefront of the verification market, meeting the growing demand for high-performance solutions in prototyping and emulation.
Industry leaders, including AMD, Arm, NVIDIA, and SiFive, have already adopted these new systems, reflecting encouraging market take-up. This success builds on Synopsys’ best-ever year in hardware, with continued momentum expected as customers seek flexibility and performance for verifying increasingly complex systems.
EDA Software and 2nm Projects
Synopsys saw a surge in design activity, particularly at advanced process nodes. The company highlighted the acceleration of 2nm projects, with Fusion Compiler standing out as the platform of choice for advanced digital design implementation. In Q1, a U.S. hyperscaler taped out a 2nm test chip exclusively using Synopsys’ design flow, and Fusion Compiler was also the preferred platform for both a U.S. HPC CPU tapeout and an Asian mobile customer’s 2nm SoC project.
Synopsys’ sign-off tools, including PrimeTime and IC Validator, continued to offer critical value to customers. PrimeTime, known for its timing, signal integrity, power, and variation-aware analysis, provided significant productivity gains, with one customer reporting a 30% faster turnaround time using multi-core scaling. IC Validator also delivered key improvements, enabling customers to achieve over 2x faster turnaround times for full-chip physical verification at 3nm and below.
AI Innovations Driving Productivity Gains
Synopsys made significant strides in integrating AI into its EDA tools, with AI-driven optimization engines delivering notable productivity improvements. In Q1, the deployment of Synopsys.ai tools saw impressive results, such as a 2x improvement in hardware utilization for a U.S. memory company using VSO.ai and a 4x improvement in turnaround time for an Asian hyperscale customer’s HPC design.
Synopsys also expanded its generative AI capabilities. New script generation features for Fusion Compiler and PrimeTime have demonstrated a 30% average productivity improvement for designers. Additionally, the generative formal verification capabilities in Verdi are providing up to a 35% productivity boost for early customers. These AI-driven advancements are expected to unlock even greater efficiencies, particularly as the industry moves toward more autonomous design workflows.
Design IP and Key Wins
While Design IP revenue saw a 17% year-over-year decline due to a strong prior-year comparison, Synopsys continues to expand its IP portfolio, particularly in the AI space. In Q1, the company launched the industry’s first Ultra Accelerator Link (UAL) and Ultra Ethernet IP solutions to address the growing need for open-standard solutions in scaling AI accelerator infrastructure.
Synopsys also captured several key design wins, including a PCIe 7.0 design with an AI infrastructure chip provider and a 224G Ethernet win with a major ecosystem player. Additionally, the company secured agreements for advanced 2nm designs, including a 112G SERDES and PCIe 6.0 agreement with a leading European telecommunications provider.
Mobile and Consumer Markets
While demand in mobile and consumer markets faced challenges, Synopsys continued to see strong design activity. A leading Asian automotive supplier adopted Synopsys’ interface, processor, and foundation IP for its next-generation products. Additionally, the company secured key design wins in mobile, including a UFS design with a company driving AI-powered PCs.
Financial Guidance
For the 2Q FY 2025, Synopsys expects revenue in the range of $1.585 billion to $1.615 billion. The midpoint of that range would represent a Y-o-Y growth of 10.0%, compared to revenue of $1.455 billion a year earlier.
For fiscal year 2025, with the pending acquisition of Ansys expected to close in the first half of 2025, Synopsys is targeting revenue of $6.775 billion +/- $0.03 billion, which is growth of 10.6% over FY 2024 revenue of $6.127 billion.
Read the full press release here.
Daniel Newman and his co-host of The Six Five Webcast, Patrick Moorhead of Moor Insights and Strategy discusses Synopsys’s earnings in their latest episode. Check it out here and be sure to subscribe to The Six Five Webcast so you never miss an episode.
Disclosure: The Futurum Group is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of The Futurum Group as a whole.
Other insights from The Futurum Group:
Synopsys Achieves Record Q4 FY 2024, Prepares for Ansys Acquisition
Six Five Webcast Talking AWS, Intel, Salesforce, Pure Storage, Synopsys, & More
Author Information
Richard Gordon is Vice President & Practice Lead, Semiconductors for The Futurum Group. He has been involved in the semiconductor industry for more than 30 years, first in engineering and then in technology and market research, industry analysis, and business advisory.
For many years, Richard led Gartner's Semiconductor and Electronics practice, building a 20-person global team covering all aspects of semiconductor industry research, from manufacturing to chip markets and end applications. Having served on Gartner's Senior Research Board and as Gartner's Chief Forecaster, Richard has extensive experience in developing and implementing methodologies for market sizing, share and forecasting, to deliver data, analysis and insights about the competitive landscape, technology roadmaps, and market growth drivers.
Richard is a sought-after technology industry analyst, both as a trusted advisor to clients and also as an expert commentator speaking at industry events and appearing on live TV shows such as CNBC.
