An Inside Look at Lattice Semiconductor’s Latest FPGAs – Six Five in the Booth

An Inside Look at Lattice Semiconductor's Latest FPGAs - Six Five in the Booth

On this episode of The Six Five – In the Booth, hosts Daniel Newman and Patrick Moorhead welcome Deepak Boppana, Sr. Director of Marketing at Lattice Semiconductor during the Lattice Developers Conference for an inside look at Lattice Semiconductor’s latest Avant FPGAs, designed for advanced connectivity like datapath applications, and flexible interface bridging and optimized compute for system expandability.

The demos include:

  • A boot time demo, and how speed contributes to security and safety
  • A low-power networking demo, and what types of applications benefit
  • A power consumption benefit demo
  • A memory transfer demo and some real-world examples of how customers can benefit from the energy-efficiency aspects

See more demos on the Lattice Semiconductor website.

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Patrick Moorhead: The Six Five is on the road at Lattice’s Developer Conference 2023 here in San Jose, California. This is their first developer conference, which both Dan and I believe is a pretty huge milestone, but very coincident with the growth of the company and the expansion of their offerings. It’s been a great conference, Dan.

Daniel Newman: Yeah, it has. And it’s good to be here on the road at the developer conference and also in the booth getting our hands on.

Patrick Moorhead: It’s always fun to talk to the executives and we do that a lot, but it’s also fun to see the technology that’s being presented at any given event and have the chance to actually look in real time, what’s the innovation, what’s going on, why does this matter? And I think that’s what we’re going to do here.

Daniel Newman: Yeah, it’s incredible. The flexibility of an FPGA and the amount of applications that it goes into is pretty incredible. And here at the show, there’s over 40 demos and sure, we’d love to go through all 40, but we’re not. We’re going to go through three really good demonstrations and we’re really, really appreciative to have Deepak here for the second year running here on The Six Five. Deepak, it’s great to see you.

Deepak Boppana: Great to see you too, Dan, Pat. And yeah, thank you for joining us at the inaugural Developer Conference and we have a really exciting lineup of demos here. And yeah, I think we can start. We are going to be focusing on different applications like AI, security, advanced connectivity, but the one we have here is really more about enabling security applications.

Patrick Moorhead: So why don’t you take us through and show us what you’re doing in this first demonstration, Deepak.

Deepak Boppana: Sure. So what we’re going to be measuring here is the boot-up time of our Avant-X FPGA. So we just launched our latest mid-range FPGAs, Avant-G and Avant-X at the Developer Conference. And this really shows the difference in boot-up time relative to similar FPGAs from other vendors.

Patrick Moorhead: And why is it important what you’re demonstrating, for those out there that are watching, why does boot time matter, especially in security applications?

Deepak Boppana: It absolutely does, both in security and safety critical applications. I think it’s just the amount of time it takes for these FPGAs to boot, you really want to be the first one to boot up on the boat and the last one to boot-off or power off because the malicious firmware attacks can happen pretty quickly. So every millisecond counts when it comes to security applications. And you can see here, basically these are commercially available development boards, and we have Avant-X from Lattice, Kintex UltraScale+ from AMD and the Arria 10 GX from Intel. And I’m basically going to just turn or configure each of these on, and you can see the amount of time it takes for them to boot up starting with the Arria 10 GX FPGA, and you can literally see it taking that long, right? 792 milliseconds, that’s quite a bit. And we do the same for the Kintex UltraScale+ FPGA, 260 milliseconds. And the Avant-X from Lattice is only 47 milliseconds. And you saw how quickly that booted up. And again, this is really important for security and safety applications.

Daniel Newman: When I saw it the first time, Deepak, I said, these are all relatively very small numbers, but you pointed out so eloquently that these are the tiny little gaps that been malicious that the hackers are looking for when they’re trying to find their way in. And so 47 versus 261 versus 792 can actually be a really meaningful gap.

Deepak Boppana: It is, absolutely is. And Lattice has a rich history in this space with even our small FPGAs, including the mock series of FPGAs that are basically the first one to turn on and the last one to turn off. And basically we are bringing all that features and expertise to the mid-range now and basically doing the same for the mid-range FPGAs as well.

Patrick Moorhead: And I have to ask, what contributes to that? Is it architecture? Is it the design of the architecture? Is it process technology, Deepak’s awesomeness that does this? What’s the magic blue crystals here?

Deepak Boppana: It absolutely is about the optimization of the architecture. So we are focused on modernizing the mid-range FPGAs from the ground up, and that’s really what enables us to achieve these types of innovations. With other FPGAs, it’s really more of a waterfall effect from the bigger FPGAs, but that’s really what it comes down to. It is really focusing on optimizing the architecture and we’re going to see some more features as well along with this boot-up time.

Daniel Newman: Well, thanks Deepak for showing us this. Let’s move on to the next demo.

Patrick Moorhead: So Deepak, we talked about the multi-variant applications that you can have with FPGAs. We’re looking at three of those. What are we looking at right now?

Deepak Boppana: So this demo is all about advanced connectivity and showcasing the low power benefits of high speed connectivity.

Patrick Moorhead: So what kind of connectivity, just if I can interject here, educate the audience based on SerDes?

Deepak Boppana: Yep. So we going to start with taking a look at the signal integrity of the SerDes on the Avant-X FPGA. So demonstrate that-

Patrick Moorhead: Real quick, this could be USB, it could be PCI, it could be name your adventure that you can do.

Deepak Boppana: Exactly. So signal integrity is really important for high speed protocols, PC express, ethernet, CPR, different kinds of networking applications. So for that, basically what you see here is a board with Avant FPGA, and it’s connected to this oscilloscope and it’s basically the same display on the monitor. So I’m going to initiate now the oscilloscope. And what you’re really seeing is the transmit eye diagram buildup on the monitor. And as you can see, it’s really wide open and it’s also the logic levels are very defined, that showcases again the signal integrity features that we have in the SerDes. Things like pre-emphasis and de-emphasis on the transmit side and decision feedback equalization on the receive side, to essentially correct for signal distortions.

Patrick Moorhead: Just you can explain to the audience what would something with a lower degree of signal integrity look like? Would there be a bunch of blue just scattered around?

Deepak Boppana: Absolutely.

Patrick Moorhead: What would it look like?

Deepak Boppana: So this eye would not be that wide open. You would see quite a bit of signal distortion that has not necessarily been corrected. So it’s really the equalization capabilities that are built into the SerDes that basically take care of those signal distortions.

Patrick Moorhead: Appreciate that.

Deepak Boppana: So that’s really more on the signal integrity side. And now as we move to this here, what we’re going to show here is really the power consumption benefits of, again, a SerDes based application, it’s high-speed ethernet designs. So all three boards are running high-speed ethernet designs. So what you’re going to see is each of these FPGAs running at the fastest ethernet speed, starting with the AMD Kintex UltraScale+ from AMD. And you can see it takes close to two watts of power just to have an ethernet loop back demo, right? And that’s running at 25 gigabits per second. And if we look at the same for the Arria 10GX FPGA from Intel, that’s only running at 10 gigabits per second. So that’s even higher close to three watts. And then the Avant-X FPGA, which is running up to 25 gig, the ethernet is significantly lower up to 2.7 times lower.

Daniel Newman: So Deepak, as we’ve asked you on other demos, one of the things I think that we’re very interested is clearly this is good and in a world where everything from sustainability to cost structures are being impacted by power consumption, it’s how… So you’re up there and there’s two very formidable companies, very well respected in the industry, but you’ve been able to achieve this. What do you attribute the ability to have such great results when it comes to power at 25 gigs here?

Deepak Boppana: Great question, right? It’s really again, all about optimization of both the SerDes power as well as the fabric and the architecture of the logic fabric. So this demo is showcasing both aspects. You have the SerDes running at that speed and you also have the soft implementation of ethernet running in the logic. So it’s really optimization of the architecture and SerDes relative to the really older FPGAs. That’s the other thing is we are really enabling or modernizing the mid-range FPGAs, whereas some of these other FPGAs haven’t been refreshed in a while.

Patrick Moorhead: But are these companies latest and greatest for this type of application?

Deepak Boppana: They are, but again, they have not necessarily been built from the ground up. So that’s really how we are differentiated.

Daniel Newman: All right, Deepak, let’s go on and show us the last demo. Deepak, we really appreciate you taking us through first demo, second demo. Let’s get to the third. What do you got here? It looks like a memory and power.

Deepak Boppana: Absolutely. Yeah. This one’s all about enabling energy efficient memory transfer. So really in a lot of edge AI applications, power consumption is really critical for battery operated and also industrial applications.

Daniel Newman: Took us three, Pat, to get to an AI demo.

Patrick Moorhead: I know. That’s good.

Deepak Boppana: That’s right. I’m saving the best for the last. And lots of developers, I think they’ve all given us feedback that one of the largest components of power consumption in AI applications is around the memory transfer from the external DRAM into the FPG, right? So that’s really what we’re going to showcase here in terms of similar, again, commercially available development boards. So starting with the Kintex UltraScale+ FPGA from AMD, you can see the total consumption of the memory subsystem, it’s greater than two watts. You can look at the same for the Arria 10 GX, close to three watts. And for Avant-G, which is again up to 2.8 times lower. And that’s really important for AI applications.

Patrick Moorhead: And Deepak, just similar to the other question, these are the latest and greatest FPGAs you can get from AMD and Intel. Is that right? That people would use in these types of applications?

Deepak Boppana: In this class of mid-range FPGAs, yes.

Patrick Moorhead: I understand. No, I appreciate that and technology understands the benefits of why this would be important, but what does this mean? Does this mean better battery life? This means less requirement for current in\ to let’s say a car or something like this?

Deepak Boppana: Exactly right. So in number of different applications could be industrial robots, that could be battery operated, could be automotive applications. It definitely kind of cuts down one of the highest components of power consumption, which is around the memory transfer. So definitely helps in multiple different Edge AI applications.

Daniel Newman: And this is a really important, given the scale of Edge AI applications, you’re showing a very limited demo. But when you’re talking about multiple systems at scale, lots of processing, this becomes economically very important. And also when it comes to companies that are trying to meet their goals when it comes to things like sustainability, these numbers really start to matter. Are you seeing that? Are customers giving you that kind of feedback?

Deepak Boppana: Absolutely, they are, So they do care about every milliwatt of our consumption in these applications. And again, we are bringing a lot of that kind of innovation into the mid-range now. And in this particular example, actually the Avant-G FPGA is the only FPGA in this class that actually supports low power DDR4 memory interface. And that really, again, is one of the reasons why it’s enabling this kind of power savings.

Patrick Moorhead: That’s great. So Deepak, you showed us a couple of things here. You’ve shown the multi-variate application of your FPGAs. You’ve ponied up with your latest and greatest, which is Avant, and I appreciate that. Now you’re showing this is three of 40 demonstrations that we’re seeing from you and your partners here. I just want to appreciate you walking us through that and dealing with some of our questions here. So I appreciate that.

Deepak Boppana: No, thank you. Thank you. And like you rightly mentioned, there’s a lot more demos, 40 plus demos, not just from Lattice, but our broader ecosystem as well. And all those videos are available on the Lattice Developer Conference portal online.

Patrick Moorhead: And Deepak, do you know where our audience can log in and get that?

Deepak Boppana: Yeah, no, that’s basically our lattice website, right? So right on the Lattice website you’ll see the registration portal and we have a lot more demos and a lot of different applications there.

Patrick Moorhead: That’s great. So this is second year in a row here, Deepak. We’re interested what you have for next year. Thank you very much.

Deepak Boppana: Looking forward to it. Thank you.

Patrick Moorhead: You got it.  So The Six Five on the road here in the booth at Lattice Semiconductor Developer Conference 2023 in San Jose, California. We appreciate you tuning in. Check out all of our Six Five content for Lattice and other folks that we have interviewed on stage, in the booth, on the road, pretty much everywhere. So for Dan and Pat, we appreciate you, hit that subscribe button and tell all your friends and family about The Six Five. Appreciate you and take care.

Author Information

Daniel is the CEO of The Futurum Group. Living his life at the intersection of people and technology, Daniel works with the world’s largest technology brands exploring Digital Transformation and how it is influencing the enterprise.

From the leading edge of AI to global technology policy, Daniel makes the connections between business, people and tech that are required for companies to benefit most from their technology investments. Daniel is a top 5 globally ranked industry analyst and his ideas are regularly cited or shared in television appearances by CNBC, Bloomberg, Wall Street Journal and hundreds of other sites around the world.

A 7x Best-Selling Author including his most recent book “Human/Machine.” Daniel is also a Forbes and MarketWatch (Dow Jones) contributor.

An MBA and Former Graduate Adjunct Faculty, Daniel is an Austin Texas transplant after 40 years in Chicago. His speaking takes him around the world each year as he shares his vision of the role technology will play in our future.


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