Efinix announced the Sapphire RV64 SoC on September 28, a 64-bit RISC-V soft processor core that runs on all Titanium and Topaz FPGAs and Trion devices T20 and above. The core adds an SV39 memory management unit for embedded Linux and a memory controller reaching 3,200 Mbps LPDDR4x for AI workloads. Futurum views the launch as a bid to make the FPGA the system processor for edge AI; at the moment, physical AI is the fastest-growing edge silicon application.
What is Covered in this Article
- Sapphire RV64 SoC, a 64-bit RISC-V soft core with a seven-stage pipeline, up to 512 KB of on-chip RAM, optional L2 cache, and an SV39 MMU for embedded Linux
- Memory controller supporting DDR3, HyperRAM, and LPDDR4x at up to 3,200 Mbps for optimized AI workloads
- Availability on all Titanium and Topaz FPGAs and Trion devices T20 and above through the free Efinity IP Manager
- Custom instruction capability that builds user-defined AI accelerators, such as matrix multiplication offload, into the soft core
- Competitive mapping against AMD MicroBlaze-V, Altera Nios V, Microchip PolarFire SoC, and Lattice in the edge AI FPGA field
The News: Efinix announced the Sapphire RV64 SoC on September 22, a 64-bit RISC-V processor core that expands the company’s Sapphire SoC suite for embedded FPGA designs. The core implements the RISC-V 64IM instruction set with optional A, F, D, C, Zba, Zbb, Zbs, and Zicbom extensions on a seven-stage pipeline, and configures with 4 KB to 512 KB of on-chip RAM, a multi-way L1 instruction and data cache, and an optional L2 cache, branch predictor, and hardware and software pre-fetchers. An optional SV39 memory management unit enables embedded Linux, and a memory controller supports DDR3, HyperRAM, and LPDDR4x operation at up to 3,200 Mbps. Sapphire RV64 is available for all Titanium FPGAs, all Topaz FPGAs, and Trion devices T20 and above, configured through the Efinity IP Manager within the free Efinity software stack.
“Sapphire RV64 was designed so customers already using our 32-bit Sapphire SoCs can scale up without re-architecting their systems,” said Tony Ngai, co-founder, Co-President, and CTO of Efinix.
RISC-V Soft Cores Go 64-Bit With Efinix Sapphire RV64
Analyst Take: The Efinix Sapphire RV64 answers a scaling problem that edge AI created. Sensor counts per system are rising, algorithms are getting heavier, and the C code that orchestrates on-device inference has outgrown 32-bit addressing, caching, and I/O in a visible share of designs. Efinix’s response is a soft 64-bit RISC-V core that a designer instantiates in FPGA fabric, scales from a single 32-bit core to a quad-core 64-bit implementation inside one tool flow, and extends with custom instructions that become AI accelerators.
The launch positions the FPGA as the system processor for edge AI rather than a companion chip waiting for an MCU or ASIC to catch up. Efinix targets its FPGAs at the robotics silicon market, which Futurum’s 1H 2026 Intelligent Devices Market Forecast projects will grow from $10.5 billion in 2025 to $16.6 billion by 2030, a 9.9% CAGR that leads every edge destination. The question is whether shipping 64-bit soft silicon today outweighs the incumbents’ scale before their roadmaps close the gap.
A Configurable 64-Bit Core Repositions the FPGA as Edge AI’s System Processor
Sapphire RV64 completes a processor range that runs from sub-4K-logic-element microcontroller footprints to quad-core 64-bit compute with multi-gigabyte memory, all delivered as soft IP in the free Efinity software stack. The 64-bit additions target the specific ceilings that 32-bit embedded cores hit in AI systems: larger addressable memory for model weights and frame buffers, deeper caching for decode-heavy control code, and an SV39 MMU that brings full embedded Linux to the fabric. The LPDDR4x controller at 3,200 Mbps matters as much as the core itself, because sensor fusion pipelines are more bandwidth-bound than compute-bound.
Efinix also offers a hardened quad-core 32-bit implementation running at roughly 1 GHz in its Titanium transceiver devices, so the soft RV64 slots into a portfolio where the customer picks the point on the area, power, and performance curve. A 64-bit core consumes meaningfully more fabric than the 32-bit version, logic cells that would otherwise implement acceleration or sensor interfaces. The business model is silicon pull. The IP is a free download, every Sapphire design win sells a Titanium, Topaz, or Trion device, and the upgrade path from RV32 keeps existing customers inside the Efinity flow instead of graduating them to an SoC vendor.
Custom Instructions Convert C Code Into Hardware Acceleration Without a Fixed NPU
The extensibility of the RISC-V ISA is the architectural reason Efinix standardized on it, and the company’s implementation exposes a custom instruction interface with 1,024 instruction IDs. Customers can instantiate a soft RISC-V core, add a custom matrix multiplication instruction, and the FPGA fabric becomes a matmul accelerator that runs an AI model far faster than the processor’s ALU could. The flow accepts model exports from TensorFlow and PyTorch, as well as the C toolchain, so a designer can partition the algorithm between software on the core and fabric-based acceleration without writing RTL for the processor itself.
Efinix told Futurum that roughly 20% of its customer designs already instantiate a RISC-V processor, and the company expects that share to keep rising. The implication is that Efinix competes with fixed-function edge NPUs on adaptability: an NPU wins on TOPS-per-watt for stable workloads, while the FPGA wins when sensors, models, and interfaces are still changing faster than ASIC design cycles. A soft core with custom instructions accelerates operators, but it will still trail dedicated NPU silicon in dense inference throughput, so Efinix’s position depends on edge AI remaining heterogeneous and in flux. RISC-V’s own matrix extension standardization also remains unsettled, which leaves each vendor’s AI instructions proprietary in practice and portability limited.
Shipping Beats Roadmaps in the 64-Bit Soft Core Race
The competitive field suggests the time could be right for Efinix. AMD’s MicroBlaze-V supports RV32 in production while its 64-bit RV64 configuration sits in early access, and AMD lists the memory management unit required for Linux as a roadmap item. Altera ships Nios V as a 32-bit processor family, with 64-bit support signaled by ecosystem partners but not yet a product, and the company’s attention is divided by its confidential IPO filing disclosed in September. Microchip’s PolarFire SoC takes the opposite approach with a hardened quad-core RV64GC subsystem that runs Linux today, a strong answer for fixed processing requirements and a weaker one where the customer wants to resize cores per design. Lattice aims its small FPGAs at control and security sockets and fields 32-bit RISC-V soft IP rather than a 64-bit application-class core.
Against that field, Efinix ships a configurable RV64 with an MMU across its entire current portfolio, from Trion T20 upward. The window is real, but it will not stay open. AMD moves early access cores to production on regular cadences, and a MicroBlaze-V RV64 with MMU on Versal and Spartan UltraScale+ volume would neutralize the differentiation quickly. Efinix’s durable advantages sit elsewhere, in an architecture the company claims runs comparable designs at half the die area and half the power of competing FPGAs, a figure that buyers should validate.
Physical AI Demand Aligns With Efinix’s Position Between the Sensor and the GPU
In Edge AI, the FPGA fits between external sensors and upstream compute with sensor processing and low-latency on-device AI in between. That socket is compounding. Lidar is migrating from autonomous vehicles to factory floors and humanoid robots, thermal sensing is joining robotic sensor suites, and each new sensor class needs programmable silicon before fixed-function alternatives exist. Beachler offered a concrete case in the briefing: a humanoid robotics customer places one FPGA per finger to fuse image and pressure sensor data, five devices per hand, in a 3.5×3.5mm package. Efinix serves these designs with system-in-package devices that co-package the FPGA with boot flash and LPDDR or HyperRAM DRAM in footprints as small as 10x10mm, a significant portion of its business today.
In Futurum’s forecast, robotics is the highest-CAGR edge silicon destination at 9.9% through 2030, while IoT sits essentially flat, projected at $30.3 billion in 2030 versus $30.6 billion in 2025. Efinix’s revenue mix tilts toward the destination that is growing. Two proof points would settle the thesis. Titanium Edge devices, which add post-quantum security capabilities and are sampling now with field trials targeted for Q4 2026, need to ship on schedule, and the humanoid and industrial design wins can produce disclosed volume production.
What to Watch
- Whether Sapphire RV64 design starts lift RISC-V attach above the roughly 20% of Efinix customer designs reported today
- Whether AMD moves MicroBlaze-V RV64 from early access to production with MMU support in 2027
- Whether Altera ships a 64-bit Nios V variant as it approaches the public markets
- Whether Titanium Edge devices with post-quantum security ship in Q4 2026 as planned
- Whether RISC-V matrix extension ratification standardizes the AI instructions FPGA vendors now implement as custom
Other Insights from Futurum:
Synopsys Autopilot Aims to Consolidate Chip Design Around One Stack
Project Suncatcher Prepares to Launch TPUs. Is Google Ahead in the Orbital AI Race?
Marvell’s 2nm Optics Target AI Scale-Up Beyond the Rack
Sources
1. Efinix® Brings 64-Bit RISC-V Performance to Embedded FPGA Designs With New Sapphire™ RV64 SoC
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
