At FMS 2026, Samsung unveiled zHBM, a concept architecture that stacks high-bandwidth memory directly on top of AI accelerators, alongside the industry’s first 400-plus-layer bonded NAND, HBM4E samples, and an HBM5 preview [1]. Samsung projects an approximately 8x performance gain over HBM5 from a next-generation interface system built on zHBM. Futurum examines whether the physics supports the bet that memory must move closer to compute.
What is Covered in this Article
- Samsung unveiled zHBM and zNAND-O concept models at FMS 2026, with zHBM stacking HBM directly above the AI accelerator and projected by Samsung to deliver approximately 8x the performance and more than 10x the memory density of HBM5.
- The company introduced V10 BV-NAND, the industry’s first 400-plus-layer NAND enabled by wafer bonding, increasing memory density by approximately 58% over the previous V9 generation.
- Samsung’s exhibited AI memory roadmap spans HBM4E samples shipping to global customers since May, an HBM5 model, LPDDR5X-PIM, and the PM1763 and BM1773 enterprise storage drives.
The News: Samsung Electronics showcased its AI memory portfolio and technology roadmap at the Future of Memory and Storage (FMS) 2026 conference in Santa Clara, California. The company unveiled the industry’s first concept models of zHBM and zNAND-O and introduced V10 BV-NAND, a 400-plus-layer NAND architecture enabled by new wafer bonding technology. Samsung zHBM vertically stacks HBM directly above AI accelerators, moving beyond conventional designs that position memory alongside the processor, and Samsung projects that a next-generation interface system incorporating zHBM will deliver approximately 8x the performance of HBM5 with more than 10x the memory density, threefold energy-efficiency gains, and a better than 50% reduction in thermal resistance. The exhibition was anchored by a keynote from Jin-Yub Lee, Executive Vice President and Head of Flash Product & Technology, and Kyungryun Kim, Vice President and Project Leader of the DRAM Design Team. Roughly 30 technologies were on display, including HBM4E samples shipping to global customers since May, an HBM5 model, LPDDR5X-PIM, the industry’s first LPDDR memory with built-in processing-in-memory, the edge-AI-optimized zNAND-O in 4- and 8-layer versions, and the PM1763 and BM1773 enterprise storage drives.
Samsung zHBM Stacks Memory on the GPU. Has HBM Run Out of Beachfront?
Analyst Take: Samsung zHBM is the most consequential announcement to come out of FMS 2026. Stacking HBM directly on top of the AI accelerator answers the question of whether memory still has to move physically closer to compute when the workarounds for scarce, expensive HBM keep improving. Our view is that Samsung’s breadth at FMS 2026 validates the memory-must-move thesis. The memory hierarchy is stratifying under AI’s bandwidth demands, with pooled and processing-in-memory tiers absorbing capacity demand while edge NAND handles inference locality. Customers will engineer around scarcity in the middle of the hierarchy, while the memory closest to the logic die will physically move.
Memory Pooling Gains Sharpen the Case for Samsung zHBM
The case for engineering around HBM is an urgent necessity as chip package sizes scale. HBM is on track to consume close to a quarter of all DRAM wafer output in 2026, and that scarcity shows up directly in accelerator bills of materials. Moonshot AI researchers have demonstrated throughput gains as high as 525% by pooling cheaper commodity memory around scarce HBM. Those gains harvest stranded capacity, yet every pooled-memory scheme still terminates at the same HBM interface at the hot end of the hierarchy. As the middle tiers absorb more of the capacity demand, the remaining bottleneck concentrates at the accelerator itself, measured in bandwidth per watt and per millimeter of die edge. Samsung zHBM attacks exactly that tier. The stakes are visible in the market itself: Futurum Intelligence projects the data center off-chip memory market will surge from $17.1B in 2025 to $96.8B in 2026 — a 466% year-over-year increase — before climbing to $260.5B by 2030.
The Interposer Beachfront Is Full, So zHBM Goes Vertical
Every HBM stack in production today talks to the GPU through the edge of the die and across an interposer, and that beachfront is exhausted. The largest AI accelerators already dedicate most of their die perimeter to memory interfaces, and each new generation fights for microns of additional shoreline. Perimeter grows linearly while compute area, and its appetite for bandwidth, grows quadratically. zHBM discards the constraint by routing thousands of connections straight down through the bond. Until recently, the idea was thermally and economically unworkable. DRAM retention and refresh behavior degrade as temperature rises, and stacking that device on a logic die dissipating a kilowatt was a non-starter. Bonding pitches were also too coarse, and no memory vendor wanted the yield liability of bonding its die to a $40,000 processor.
What changed is the maturity of wafer bonding and the exhaustion of cheaper alternatives. Samsung’s claimed halving of thermal resistance, a vendor-supplied figure, is the number that most needs independent validation. zHBM also supports customer-specific IP integrated into the interlayer between the memory and accelerator, echoing the custom HBM base-die trend. As a result, memory is graduating from a commodity component into a co-designed silicon, which is where the margin is going.
V10 BV-NAND Turns a Known Concept Into a Supply Race
The physics problem with 400-layer NAND is well understood. Channel holes must be etched through the entire stack at aspect ratios approaching those of a skyscraper, and the high temperatures required to build the memory array damage the CMOS logic beneath it. Wafer bonding sidesteps both problems by manufacturing the array and the logic on separate wafers and bonding them afterward. Every major supplier knows the trick. Kioxia and SanDisk have discussed bonded architectures, and YMTC has shipped its Xtacking variant for years.
Samsung’s achievement is productization. V10 BV-NAND is the first announced 400-plus-layer NAND built on wafer bonding, with an approximately 58% density gain over V9, arriving 13 years after Samsung introduced the industry’s first V-NAND at the 2013 Flash Memory Summit. The differentiator at these layer counts lives in bonding interface yield and alignment precision across a full wafer. FMS is a venue for industry firsts, and this one deserves scrutiny in proportion to its ambition. Until Samsung attaches production timelines and customer qualifications, V10 BV-NAND remains a statement of capability.
Samsung Is Arming Every Version of the Proximity Bet
zHBM has company. Qualcomm’s AI250 claims more than 10x effective memory bandwidth from near-memory computing, based on Qualcomm’s internal estimates, and Samsung’s own LPDDR5X-PIM is the industry’s first LPDDR memory with processing-in-memory built in. Architecturally distinct products are converging on the conclusion that the cost of moving data now dominates the cost of computing on it. Samsung is positioning itself as the supplier that makes every version of this bet possible. If near-memory architectures win, Samsung sells the LPDDR and the PIM. A stacked-memory future sells zHBM and the bonding services, while conventional HBM demand keeps HBM4E shipping today, with HBM5 behind it.
That posture is backed by scale: Samsung led the data center memory market with a 34.0% revenue share in Q4 CY2025, ahead of SK Hynix at 29.8% and Micron at 17.9%, according to Futurum’s 1H 2026 Data Center Semiconductor Forecast. This aggressive posture fits a memory vendor watching its product migrate up the value stack. The company’s position as the only integrated device manufacturer spanning memory, foundry, and advanced packaging sharpens the pitch. It’s a one-stop turnkey message at FMS 2026 that promises integrated development from product design through mass production. When memory is bonded directly to the accelerator, the memory maker and the packager effectively must share one cleanroom, because every handoff becomes a yield event. The bear case is that Samsung’s turnkey pitch has yet to dislodge customers from TSMC’s packaging orbit, and single-vendor lock-in remains a live customer fear. zHBM shifts that calculus further than any prior Samsung offering, because the architecture itself makes disaggregated supply chains structurally harder.
Thermal Extraction Will Set the Samsung zHBM Timeline
Three gating items stand between the zHBM concept and production. Hybrid bonding pitches must scale well below 10 microns at production yield across full DRAM stacks. Heat extraction paths must pull on the order of a kilowatt through a DRAM stack without degrading retention, and test methodologies must prove a die is good before it is irreversibly bonded to something expensive. We judge thermals the tallest hurdle. Bonding pitch is scaling on a predictable equipment roadmap, and known-good-die testing is an engineering and economics problem. Moving a kilowatt through devices whose data retention degrades with every additional degree is a materials science problem, and materials science resists roadmaps. The concept model framing is appropriate for a destination announcement. Samsung has planted its flag earlier and more completely than any competitor, and volume shipment will require breakthroughs from its supply chain: bonder and metrology equipment makers, thermal interface material formulators, and test vendors.
What to Watch
- Whether NVIDIA, AMD, and hyperscaler custom-silicon programs allocate die area and thermal budget for stacked memory in next-generation accelerator roadmaps, and how quickly SK hynix and Micron answer with vertical-stacking concepts of their own.
- Progress on the three zHBM gating technologies will set the production timeline more than any design decision.
- V10 BV-NAND production timing and customer qualification against Kioxia, SanDisk, and SK hynix 400-plus-layer roadmaps, where the gap between an FMS industry first and volume supply decides NAND leadership.
Sources
1. Samsung Unveils Next-Gen 3D-Memory Vision at FMS 2026, Charting the Future of AI Infrastructure, Samsung, August 2026
Declaration of generative AI and AI-assisted technologies in the writing process: This content has been generated with the support of artificial intelligence technologies. Due to the fast pace of content creation and the continuous evolution of data and information, The Futurum Group and its analysts strive to ensure the accuracy and factual integrity of the information presented. However, the opinions and interpretations expressed in this content reflect those of the individual author/analyst. The Futurum Group makes no guarantees regarding the completeness, accuracy, or reliability of any information contained herein. Readers are encouraged to verify facts independently and consult relevant sources for further clarification.
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
