Analyst(s): Richard Gordon
Publication Date: March 3, 2025
Synopsys has expanded its Hardware-Assisted Verification (HAV) portfolio, unveiling HAPS-200 prototyping and ZeBu-200 emulation systems to address the growing complexities of AI, high-performance computing (HPC), and multi-die semiconductor designs. Additionally, ZeBu Server 5 has been enhanced to scale beyond 60 billion gates, highlighting Synopsys’ commitment to tackling the verification challenges posed by increasingly software-defined systems.
What is Covered in this Article:
- Synopsys expands its HAV portfolio with HAPS-200, ZeBu-200, and ZeBu Server 5 to address AI and multi-die complexity.
- Multi-die adoption surging, with 90% of HPC AI designs and 70% of PC processors, is expected to integrate multi-die architectures by 2027.
- EP-Ready Hardware enables seamless reconfiguration between emulation and prototyping, improving efficiency.
The News: Synopsys has expanded its Hardware-Assisted Verification (HAV) portfolio with the introduction of the HAPS-200 prototyping system, ZeBu-200 emulation system, and an upgraded ZeBu Server 5. These innovations address the increasing complexity of AI, high-performance computing (HPC), and multi-die semiconductor designs.
Built on Synopsys’ Emulation and Prototyping (EP-Ready) Hardware, the new solutions offer seamless reconfiguration between prototyping and emulation, helping customers maximize their return on investment. Industry innovators such as AMD, Arm, NVIDIA, and SiFive are already leveraging these technologies to accelerate chip development and bring products to market faster.
Key updates include:
- HAPS-200 Prototyping System: Delivers a 4x boost in debug performance compared to HAPS-100, supports mixed HAPS-200/100 environments, and scales up to 10.8 billion gates.
- ZeBu-200 Emulation System: Expands design capacity to 15.4 billion gates, offers 2x higher runtime performance, and delivers 8x better debug bandwidth than the ZeBu EP2.
- ZeBu Server 5 Upgrade: Now scales beyond 60 billion gates, optimizing multi-die verification while reducing both compile times and compute resource demands.
- Synopsys Virtualizer Upgrade: Introduces multi-threading support, significantly accelerating software bring-up – now capable of booting a full Android OS in under 10 minutes.
Synopsys Introduces New HAV Tools to Address Growing SoC Design Complexity
Analyst Take: With the expansion of its HAV portfolio, Synopsys is strategically reinforcing its vision for AI-driven electronic design automation (EDA), multi-die architectures, and software-defined silicon. The surge in AI workloads, increasing investments in hyperscaler chips, and the growing complexity of semiconductor verification are pushing the industry toward more scalable and flexible solutions. By integrating its modular, reconfigurable verification technology, Synopsys strengthens its competitive position – especially as it works to finalize its acquisition of Ansys.
AI and Multi-Die Complexity Are Reshaping EDA – Synopsys Is Responding
AI workloads, multi-die semiconductor designs, and domain-specific computing are reshaping verification requirements. By 2027, it’s projected that 90% of HPC AI designs and 70% of PC processors will incorporate multi-die architectures, leading to an explosion in gate counts – far exceeding what traditional verification methods can handle.
ZeBu Server 5’s ability to scale beyond 60 billion gates directly addresses these emerging challenges, ensuring robust verification for next-generation AI and multi-die system-on-chips (SoCs). Meanwhile, the rapid adoption of AI-driven workloads is accelerating market cycles, forcing semiconductor companies to shorten design and validation timelines to stay competitive. As demand for high-performance AI and multi-die architectures grows, companies must complete verification faster to meet shrinking time-to-market windows. Synopsys’ hybrid HAV methodology, coupled with its EP-Ready Hardware, offers the flexibility and scalability necessary to keep pace.
Synopsys’ AI-powered DSO.ai, VSO.ai, and TSO.ai tools have already been instrumental in over 700 tape-outs, optimizing 90% of SoC blocks and dramatically cutting down design cycle times. The latest HAV advancements further boost Synopsys’ leadership in AI-driven EDA, ensuring chipmakers can validate complex architectures faster and at scale.
EP-Ready Hardware: Strengthening Synopsys’ Competitive Edge
The new HAPS-200 and ZeBu-200 systems utilize EP-Ready Hardware, allowing engineers to transition between emulation and prototyping. This eliminates the need for dedicated verification systems, reducing both costs and resource inefficiencies.
Historically, companies had to make early predictions about their verification needs – often leading to underutilized hardware or costly expansions. EP-Ready Hardware mitigates these risks by enabling real-time adaptability to project demands, maximizing efficiency and return on investment.
Given the sheer complexity of AI-driven and multi-die SoCs, verification and software development now require quadrillions of cycles across simulation, emulation, and prototyping. With ZeBu-200 and HAPS-200, customers such as AMD, NVIDIA, and Arm can optimize their verification workflows without the burden of excessive upfront hardware investments.
Final Thoughts: A Strategic Expansion Aligned with Market Trends
Synopsys’ expansion of its HAV portfolio isn’t just another product update – it’s a strategic move aimed at tackling some of the semiconductor industry’s most complex challenges. As multi-die architectures, AI-driven workloads, and software-defined silicon become the new standard, the demand for scalable, AI-powered verification solutions has never been more pressing. By combining hybrid verification, modular scalability, and software acceleration, Synopsys is not only addressing the growing complexity of semiconductor design but also helping chipmakers bring next-generation products to market faster.
Despite strong competition from Cadence and Siemens, Synopsys’ ability to execute its AI-driven, scalable verification strategy will be a key differentiator in maintaining its competitiveness. The company’s pending $35 billion acquisition of Ansys further reinforces this approach, expanding its verification capabilities beyond electrical validation to include multi-physics simulation – a crucial step in bridging the gap between chip-level and system-level verification.
With early adoption from industry leaders such as AMD, NVIDIA, and Arm, along with a clear roadmap for AI-enhanced electronic design automation (EDA), Synopsys is well-positioned to drive the next wave of high-performance semiconductor verification and solidify its place at the forefront of the industry.
What to Watch:
- Cadence and Siemens’ response as Synopsys strengthens its verification leadership with AI-driven scalability and hybrid verification capabilities.
- Potential impact of the Ansys acquisition, as integrating multi-physics simulation could redefine verification beyond electronic validation, altering market dynamics.
- Adoption rates among semiconductor leaders, particularly AMD, NVIDIA, and Arm, which will indicate whether Synopsys’ modular HAV methodology becomes an industry standard.
- Regulatory and geopolitical factors, including trade restrictions and supply chain challenges, potentially influencing verification hardware adoption.
See the complete press release on Synopsys’ expansion of its Hardware-Assisted Verification portfolio with HAPS-200 and ZeBu-200 on the Synopsys website.
Disclosure: The Futurum Group is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of The Futurum Group as a whole.
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Author Information
Richard Gordon is Vice President & Practice Lead, Semiconductors for The Futurum Group. He has been involved in the semiconductor industry for more than 30 years, first in engineering and then in technology and market research, industry analysis, and business advisory.
For many years, Richard led Gartner's Semiconductor and Electronics practice, building a 20-person global team covering all aspects of semiconductor industry research, from manufacturing to chip markets and end applications. Having served on Gartner's Senior Research Board and as Gartner's Chief Forecaster, Richard has extensive experience in developing and implementing methodologies for market sizing, share and forecasting, to deliver data, analysis and insights about the competitive landscape, technology roadmaps, and market growth drivers.
Richard is a sought-after technology industry analyst, both as a trusted advisor to clients and also as an expert commentator speaking at industry events and appearing on live TV shows such as CNBC.
