Synopsys, Cadence, and Siemens simultaneously announced expanded certified design flows, IP portfolios, and AI-driven capabilities on Samsung Foundry’s 2nm class processes at SAFE Forum 2026. The triple announcement reveals how Samsung’s foundry renaissance creates growth vectors for three EDA ecosystems.
What is Covered in This Article:
- Synopsys, Cadence, and Siemens release competing Samsung 2nm certifications simultaneously
- Samsung’s foundry momentum from NVIDIA Groq 3, AMD HBM4, and Tesla AI5 engagements
- Diverging differentiation across multiphysics, NVLink-C2C IP, and photonics verification
- AI-driven design automation approaches from both vendors on Samsung’s platform
- Advanced packaging approaches across all three vendors for multi-die AI silicon
The News: Synopsys announced at Samsung Advanced Foundry Ecosystem (SAFE) Forum 2026 on May 28, 2026, production-ready AI-powered digital and analog design flows for Samsung’s third-generation 2nm class process, expanded certified interface IP, silicon-based test capabilities delivering up to 20% test efficiency improvements through TestMAX with AI-assisted ATPG, and new multiphysics signoff solutions including PrimeShield Process Sensitivity Analysis and Totem-SC electromigration and IR drop analysis certified on second-generation 2nm and 4nm class processes. Synopsys also validated its 3DIC Compiler on Samsung’s Hybrid Copper Bonding 3D test chip and expanded its IP portfolio spanning UCIe, PCIe 7.0, 112G/224G, LPDDR6, and DDR5 MRDIMM Gen2 across processes from 14nm through second-generation 2nm.
On the same day, Cadence announced a multi-year collaboration with Samsung Foundry, delivering Memory and Interface IP, agentic AI-optimized GPU-accelerated EDA flows, and NVIDIA NVLink-C2C-enabled interconnect certified on Samsung’s second-generation 2nm process. Cadence’s announcement included an NVIDIA endorsement, with NVIDIA Vice President Timothy Costa citing Cadence’s GPU-accelerated design flows on Samsung’s 2nm platform for “optimizing the performance and delivery of next-generation AI architectures, and high-bandwidth interconnects.” Cadence also named Ambarella as a customer deploying Cadence flows on Samsung’s second-generation 2nm for edge AI platforms and announced its Integrity 3D-IC Platform certification on Samsung’s 3D Cube-H architecture.
Siemens also announced continued collaboration with Samsung Foundry at the same event, certifying its EDA solutions for Samsung’s next-generation 2nm process across photonic integrated circuit verification, physical verification, and layout optimization through Calibre, design-for-test through Tessent, advanced packaging solutions for Samsung’s 2.3D Cube-E platform exceeding two million pins, and digital implementation through Aprisa, certified for leading-edge process nodes. “Samsung Foundry continues to work closely with Siemens to support customers with robust, manufacturing-ready design flows across advanced process technologies,” said Hyung-Ock Kim, vice president and head of the Foundry Design Technology Team, Samsung Electronics, in a statement that notably echoed the same executive’s separate endorsements of both Synopsys and Cadence at the same event.
Samsung’s 2nm Advance Draws on EDA Innovation from Cadence, Siemens, and Synopsys
Analyst Take: The simultaneous announcements from Synopsys, Cadence, and Siemens mark the maturation of Samsung Foundry’s EDA ecosystem strategy for 2nm and Physical AI, reinforcing the design starts from customers whose tool preferences and architectural priorities span all three vendors. Samsung’s foundry is in the midst of a resurgence due to customer engagements like NVIDIA’s Groq 3 Language Processing Unit and improved HBM4 testing. AMD has signed an agreement for HBM4 supply and potential foundry services while Tesla executes a dual-foundry AI5 strategy targeting record chip volumes. This customer density relies on EDA innovations operating at full certification depth to serve the heterogeneous demands of its expanding design-start pipeline. The range of contributions suggests that Samsung’s platform is diverging into viable paths to silicon for advanced logic, memory, photonics, and Physical AI, each optimized for distinct architectural priorities.
Synopsys’s Third-Generation Lead Versus Cadence’s NVIDIA and Physical AI IP
Synopsys’s announcement of production-ready flows on Samsung’s third-generation 2nm class process establishes a generational certification lead, while Cadence counters with certified NVIDIA NVLink-C2C interconnect IP purpose-built for accelerated computing, and Siemens introduces capabilities neither competitor offers: photonic integrated circuit verification and ultra-high-pin-count packaging automation exceeding two million pins. Synopsys differentiates through process intimacy and silicon-validated DTCO feedback loops, while Cadence differentiates through system-level interconnect IP with the largest possible customer for Samsung. Synopsys’s PrimeShield results — 2.7% frequency improvement within 5% leakage current degradation validated against silicon feedback — represent empirical evidence of process maturity that requires sustained joint engineering investment with Samsung across multiple tape-outs.
Cadence’s NVIDIA endorsement, by contrast, positions its flows as the natural choice for customers designing within the NVIDIA accelerated computing stack, where NVLink-C2C is the dominant chip-to-chip interconnect standard. For Samsung Foundry, this suggests that customers arriving from the NVLink ecosystem may gravitate toward Cadence’s certified flows, while customers prioritizing power-performance optimization at the most advanced nodes may prefer Synopsys’ deeper process co-optimization. Physical AI collaboration is also a strong point for Cadence, given its collaboration with Samsung on its Chiplet Spec‑to‑Packaged‑Parts ecosystem. Siemens’s expansion into photonic IC verification on Samsung’s platform addresses a design domain — optical interconnects for AI data centers — where neither Synopsys nor Cadence has announced equivalent Samsung-certified capabilities. Samsung’s competitive position against TSMC is strengthened not by choosing one EDA partner over the others, but by maintaining an ecosystem at full certification depth to maximize the addressable universe of potential design starts.
Samsung’s Customer Constellation Demands Ecosystem Depth
The convergence of NVIDIA Groq 3 LPU fabrication on Samsung’s 4nm, AMD’s HBM4, and potential foundry services, Tesla’s dual-foundry AI5 program, and Ambarella’s edge AI designs creates a customer constellation whose diversity of architectural requirements structurally necessitates complementary EDA capabilities. Groq partnered with Samsung’s foundry design service team, utilizing its Tensor Streaming architecture on the SF4X process, a workflow requiring mature EDA certification at the 4nm node, precisely where Synopsys has now certified Totem-SC for power integrity analysis.
Cadence’s naming of Ambarella as a customer deploying on Samsung’s second-generation 2nm for edge AI platforms demonstrates that its certification is already translating into customer traction beyond the NVIDIA ecosystem. Tesla’s nine-month generational design cycles demand AI-powered automation from whichever EDA vendor its engineers select, creating pressure on both Synopsys and Cadence to demonstrate that their Samsung-certified flows can support accelerated tape-out cadences. The Tesla relationship may be a net positive for Synopsys, given their historic collaboration, though Cadence IP may prove useful for successive robotics chip designs.
Samsung’s HBM4 further expands the surface area where both vendors’ tools must operate, as memory controller IP and signoff for high-bandwidth interfaces become qualifying requirements. The net effect is that Samsung’s foundry competitiveness is now measured not by process metrics alone but by the combined depth and breadth of its EDA ecosystem.
3DIC and Advanced Packaging: Parallel but Distinct Integration Strategies
3D chip design automation remains an unsolved problem that can yield disproportionate benefits to the EDA vendor that collaborates most closely with foundries on advanced packaging. Synopsys’s validation of 3DIC Compiler on Samsung’s Hybrid Copper Bonding test chip and Cadence’s certification of its Integrity 3D-IC Platform on Samsung’s 3D Cube-H architecture represent parallel approaches to the same heterogeneous integration challenge, each optimized for different aspects of the multi-die design problem. Synopsys positions 3DIC Compiler as a unified exploration-to-signoff platform that replaces manual, margin-based approaches with automated AI-driven system optimization, targeting the full complexity of thermal, electrical, and mechanical analysis across 3D-stacked dies. Cadence’s Integrity 3D-IC Platform, paired with its NVIDIA NVLink-C2C certification, emphasizes high-bandwidth chip-to-chip connectivity. Siemens’s Innovator3D IC differentiates on scale — automating daisy-chain netlist generation for designs exceeding two million pins — and on early-stage floorplanning that enables rapid response to design changes before physical implementation begins. The support of Hyung‑Ock Kim at Synopsys Converge for collaboration on Copper Hybrid Bonding technology, and in this announcement, suggests that Synopsys’ 3DIC Compiler can extend the company’s historical lead in design synthesis to this new era.
Samsung faces the challenge of keeping pace with TSMC on heterogeneous integration capabilities to compete for multi-die design starts. The presence of both platforms certified on Samsung’s advanced packaging architectures gives customers a genuine choice in how they approach 3D integration, reducing the risk that packaging complexity becomes a barrier to Samsung design adoption. Advanced packaging certification is emerging as a third axis of EDA competition alongside logic design flows and IP portfolios, with both Synopsys and Cadence recognizing that Samsung’s 3D packaging roadmap is inseparable from its foundry competitiveness.
Read the full press release on the Synopsys website.
What to Watch:
- Whether Samsung’s third-generation 2nm class process attracts design starts before Cadence and Siemens achieve equivalent certification, or whether customers consolidate on the second-generation node, where both vendors offer validated flows
- The extent to which Cadence’s NVIDIA NVLink-C2C IP on Samsung 2nm captures design starts from NVIDIA ecosystem customers that might otherwise default to Synopsys’ broader node coverage or Siemens’ specialized verification
- How NVIDIA’s Groq 3 LPU manufacturing success on Samsung 4nm influences EDA tool selection for subsequent inference silicon generations migrating to more advanced nodes
- How Tesla’s dual-foundry AI5 strategy validates competing AI-powered EDA paradigms
- Whether AMD’s potential foundry services expansion with Samsung creates tool selection dynamics that favor one EDA vendor’s flow or demands multi-vendor interoperability across all three
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
