The News: Marvell, a provider of data infrastructure semiconductor solutions, announced last week an extension of their long term partnership with TSMC, a top-tier dedicated semiconductor foundry, to deliver a silicon portfolio for the data infrastructure market leveraging the industry’s most advanced 5 nanometer (nm) process technology. Next-generation infrastructure is proving critical to the global economy. It’s what’s keeping the world connected, businesses running and information flowing.
With this collaboration, Marvell and TSMC are advancing the essential technology underpinning this infrastructure to provide the storage, bandwidth, speed, and intelligence that tomorrow’s digital economy demands – with the added customer benefit of significant energy efficiency. Built in partnership with TSMC on the most advanced process technology currently in volume production, Marvell’s new 5nm portfolio is designed to enable silicon innovation for the infrastructure market. Read the full Marvell press release here.
Marvell and TSMC Push Data Infrastructure Boundaries with 5nm Process
Analyst Take: The extension of the alliance between Marvell and TSMC targets locking in high-performance compute, networking, and security technologies at the silicon-level to drive data infrastructure innovation for a vast array of emerging applications. With the move, Marvell is touting its portfolio’s latest capabilities.
These capabilities include Marvell’s Ethernet connectivity solutions designed to deliver high-performance, low-power network connectivity that ranges from cloud data centers to the rugged environments of the automotive industry. Marvell’s OCTEON platform delivers the ARM-based high-performance compute architecture key to developing embedded infrastructure applications that address a wide array of fixed and wireless networking devices including switches, routers, security gateways, firewalls, and network monitoring solutions.
Marvell needed to extend its relationship with TSMC to showcase the multiple designs of its 5nm portfolio encompassing the service provider, enterprise, automotive, and data center market segments. By the same measure, TSMC needed to extend its relationship with Marvell to tout its 5NP process, an enhanced version of TSMC’s 5nm technology which is capable of delivering around 20 percent faster speed or 40 percent power reduction compared to the previous 7nm generation.
Marvell and TSMC’s Partnership Extension Injects Innovation across the Data Infrastructure Realm
The Marvell-TSMC alliance now enables the infrastructure industry’s process node cadence to align more tightly with the consumer and high-performance realms. As a result, Marvell strengthens its capacity to push new advances and innovations across the infrastructure industry in areas like power efficiency gains and new level-set performance.
The alliance also provides roadmap stability for OEMs and partners for 3nm process designs and beyond. As Marvell and TSMC, as well as the entire semiconductor industry approach the 3nm threshold, the question of what comes next is germane. For years, the semiconductor industry has advocated that the smaller the node number the better the technical capabilities. However, using the transistor gate length metric (e.g., 12nm, 10nm, 7nm, 5nm, 3nm, etc.) is running up against the sheer physics of literally counting atoms that constitute the gate length (i.e., 12 atoms or less now for 3nm and sub-3nm). So what comes next?
TSMC is proposing a new approach, co-authoring “A Density Metric for Semiconductor Technology” including authors from MIT, Stanford, and UCal-Berkeley. The proposal calls for a broader density-metric, defined as the LMC density metric, which simultaneously accounts for logic, memory, and connectivity (i.e., packaging/integration) technologies. Intel is also indicating support for using an LMC density metric approach.
The LMC approach can also accommodate FinFET (Fin Field Effect Transistor) advances. FinFET is a type of non-planar or 3-D transistor used in the development of recent processors. By using a conducting channel that rises above the level of the insulator, FinFET creates a thin, fin-shaped silicon structure described as a gate electrode. The fin-shaped electrode allows multiple gates to operate on a single transistor, enabling the extension of Moore’s Law over the last few years.
The proposed LMC approach also plays to Marvell’s strong suit in design logic, the “L” component. I see Marvell’s ability to optimize design logic has enabled the company to differentiate its OCTEON platform in key metric areas such as power conservation and scalability against key rivals such as Broadcom and Intel. As such, I believe Marvell needs to join TSMC in pushing for the LMC density metric to both showcase its own portfolio differentiators as well as ease marketing confusion as the industry approaches the sub-3nm realm.
Marvell and TSMC 5N Collaboration: Concerns and Supply Chain Considerations
On the concern side, Marvell and TSMC’s ability to deliver impressive 5N breakthroughs such as 20% faster speeds and 40% power reduction comes with increased costs. In order to attain such metrics, mask costs go up noticeably, reducing the near-term addressable market for 5nm silicon technology. However, I anticipate there is a critical mass of top-tier OEMs that can afford the extra costs to help push 5N technology across the ecosystem and toward swifter mainstream adoption in 2021 and beyond.
Also, I believe there are increasingly plausible scenarios for Softbank to sell its ownership of Arm to a Marvell competitor such as NVIDIA. Such a move could oblige Marvell to re-think its relationship with Arm since NVIDIA (or another rival acquiring Arm) would logically have the inside track to leverage Arm-based innovations. At the least, it’s a competitive dynamic I will be closely monitoring.
Of interest is TSMC’s plan to build a $12 billion plant in Arizona, to open by 2024. The completion of the plant lessens supply chain concerns related to U.S.-China geo-political developments and I expect this would solidify the long-term supply chain credentials of the Marvell-TSMC alliance.
Marvell and TSMC 5N Collaboration: Key Takeaways
Of note, Marvell is committed to continue working with GLOBALFOUNDRIES into the foreseeable future on solutions that do not require sub-12nm capabilities. After completing the $650 million acquisition of Avera Semiconductor’s ASIC assets, Marvell entered into a long-term wafer supply agreement with GLOBALFOUNDRIES. GLOBALFOUNDRIES made the strategic decision to focus on specialized processes and forego further investments in 7nm fabrication processes, automatically precluding any development work on sub-7nm processes such as 5nm.
Overall, I foresee the Marvell-TSMC collaboration paying long-term dividends for both companies. Marvell fortifies its ability to further differentiate the OCTEON portfolio in areas such as gate density, performance, and power efficiencies to drive innovation across the data infrastructure market. In turn, TSMC validates its 5nm foundry credentials to further boost its supply chain influence throughout the semiconductor market – a win-win collaboration for both companies.
Futurum Research provides industry research and analysis. These columns are for educational purposes only and should not be considered in any way investment advice.
Other insights from Futurum Research:
Marvell Crystallizes its Custom ASIC Portfolio and Market Message
Marvell’s Borderless Enterprise Portfolio Gets Safer and Smarter
An Insider’s Look at the Current Semiconductor Market – The Six Five Insiders Edition
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Author Information
Ron is an experienced, customer-focused research expert and analyst, with over 20 years of experience in the digital and IT transformation markets, working with businesses to drive consistent revenue and sales growth.
Ron holds a Master of Arts in Public Policy from University of Nevada — Las Vegas and a Bachelor of Arts in political science/government from William and Mary.
