Marvell Advances Chip-Level Power Integration for AI and Cloud Efficiency

Marvell Advances Chip-Level Power Integration for AI and Cloud Efficiency

Analyst(s): Ray Wang
Publication Date: June 23, 2025

Marvell’s latest PIVR power offerings aim to enhance AI and cloud infrastructure performance by increasing power density and cutting transmission losses. The company has partnered with leading vendors to support kilowatt-class compute platforms with more compact, efficient voltage regulation.

What is Covered in this Article:

  • Marvell introduced its Package Integrated Voltage Regulator (PIVR) power offerings, which better manage the flow of electricity to semiconductors.
  • The offering supports tighter integration of power delivery with the processor, improving performance and power efficiency.
  • Marvell claims up to 2x higher current density and 85% lower transmission losses with PIVR.
  • Key industry players, such as Infineon, MPS, Empower, Ferric, and Endura Technologies, have partnered with Marvell on PIVR.
  • The offering forms part of Marvell’s broader custom cloud strategy focused on delivering optimized infrastructure.

The News: Marvell Technology (NASDAQ: MRVL) has introduced its Package Integrated Voltage Regulator (PIVR) power offerings aimed at boosting performance, efficiency, and ROI for hyperscalers running AI and cloud systems. These ready-to-use offerings move away from the usual board-level power setups, bringing power regulation closer to the processor with integrated silicon chips.

PIVR shortens the final leg of voltage conversion, offering better voltage control and slashing power loss by up to 85%. It delivers twice the current density of standard designs and supports 4-kilowatt and beyond compute platforms. Partners on this include Infineon, MPS, Empower Semiconductor, Ferric, Photeon, and Endura Technologies.

Marvell Advances Chip-Level Power Integration for AI and Cloud Efficiency

Analyst Take: Marvell’s launch of its validated PIVR offerings is a move in chip-level power integration, especially as hyperscalers look for power-efficient solutions. Energy remains a key bottleneck for hyperscalers and data center buildouts. Marvell is betting on PIVR as a core piece of future AI and cloud infrastructure, building on custom silicon and strong partnerships across the power delivery space.

Shift from Board-Level to Package-Level Design

Switching from traditional board-level to integrated voltage regulation near or under the chip cuts down electrical path lengths and losses. With PIVR, the voltage can drop from high input to below 1V with better control. Being close to the processor helps it respond faster to changing current demands and frees up board space, which allows more compute power per rack. These changes make PIVR a practical option for powerful new compute platforms.

Quantifiable Power Efficiency Improvements

PIVR shows clear performance improvements, with Marvell citing up to 85% less transmission loss, 15% lower overall system power use, and 60% less power noise. In massive data centers, small gains add up fast. Better waveform filtering and voltage control also help maintain steady performance during demanding AI tasks. In addition, the ability to adjust voltage in real time gives more flexibility with power management. All of this boosts performance per watt in AI and cloud systems.

Strong Ecosystem Support

Marvell has brought together a solid group of partners to help scale PIVR. Infineon adds high-density modules and packaging, while MPS contributes power delivery know-how. Empower, Endura, Ferric, and Photeon offer thermal management and system testing expertise. This teamwork lowers integration risks and speeds up adoption in custom XPU rollouts. The broad support shows that PIVR is ready for real-world use.

Strategic Fit in Marvell’s Custom Cloud Platform

PIVR fits right into Marvell’s bigger custom cloud game plan, which blends chip packaging, interconnects, memory, and power control. Marvell aims to deliver system-wide performance with silicon built specifically for hyperscale needs. By building PIVR into its chips, the company tightens its grip on the power-performance-efficiency balance. This end-to-end approach helps Marvell get more value out of each chip and build longer-term partnerships, aiming to position itself more competitive in the XPU landscape.

What to Watch:

  • Marvell’s ability to scale PIVR deployment across different AI compute architectures and maintain integration efficiency
  • Adoption timelines and ecosystem readiness for PIVR across hyperscaler platforms
  • Execution strength in coordinating partnerships with Infineon, MPS, Empower, Ferric, and others for the production ramp
  • Customer traction for PIVR in upcoming custom XPU engagements and kilowatt-class systems

See the complete press release on Marvell’s launch of PIVR power offerings on the Marvell website.

Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.

Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.

Other insights from Futurum:

Marvell Q1 FY 2026 Results Driven by Custom Silicon and Data Center Momentum

Marvell Debuts Custom HBM Compute Architecture

OFC 2025: Marvell Interconnecting the AI Era

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