Analyst(s): Ray Wang
Publication Date: September 25, 2025
Synopsys and TSMC have broadened their collaboration across advanced EDA flows, IP, and multi-die enablement, with certifications on nodes from N3 to A16 and AI-optimized photonic design flows. The partnership targets AI acceleration, high-speed communications, and advanced computing.
What is Covered in this Article:
- Synopsys and TSMC’s expanded collaboration across certified flows, IP, and photonic design.
- Use of AI software to reduce chip design time and power consumption.
- Integration of multiphysics simulation, 3DIC Compiler, and IP for customer tape-outs.
- Certifications spanning TSMC’s N3, N2P, and A16 processes for AI, HPC, and automotive.
The News: Synopsys announced a deeper collaboration with TSMC to provide certified EDA flows, broad IP portfolios, and advanced multi-die enablement across nodes, including N3C, N3P, N2P, and A16. The work also extends into AI-driven photonic flows on the TSMC-COUPE platform, multiphysics simulation, and the 3DIC Compiler platform, which has already enabled multiple customer tape-outs. TSMC is using AI software from Cadence and Synopsys to design more energy-efficient AI chips. Demonstrations showed AI completing designs in minutes that previously took engineers two days, cutting power consumption in AI chips by up to ten times.
Can Synopsys and TSMC Accelerate Next-Gen Chip Design With AI?
Analyst Take: The collaboration between Synopsys and TSMC shows how certified design flows, multiphysics simulation, and IP portfolios can speed up the design of AI, multi-die, and photonics-enabled chips. The use of AI-assisted design addresses challenges around time-to-market, energy efficiency, and complexity in advanced semiconductor processes. As TSMC advances toward its N2 process and eventually the A16 node, its deepening collaboration with Synopsys is shaping up to be a mutually beneficial partnership, building up its existing partnership in previous nodes. TSMC has reportedly already secured more than 15 customers for its high-value N2 process, and we expect the A16 node—likely ramping in 2027—to gain similar momentum. This should provide long-term tailwinds for Synopsys.
Another key pillar of this partnership is advanced packaging, particularly SoIC-X, which is set to become TSMC’s cornerstone 3D packaging technology. Continued collaboration in advanced packaging not only strengthens TSMC’s technology leadership but also expands Synopsys’ business opportunities in this critical growth area.
AI-Driven Design Efficiency
TSMC demonstrated how Synopsys and Cadence AI tools significantly shorten design cycles. Work that used to take engineers two days was completed by AI in about five minutes, showing a clear improvement in speed and accuracy. This is especially important for AI servers that consume up to 1,200 watts, with AI-driven workflows helping integrate chiplets while lowering power use. Certification of AI-assisted photonic flows on the TSMC-COUPE platform further builds on these capabilities, improving both productivity and efficiency in chip design.
Certified Flows Across Advanced Nodes
The collaboration covers TSMC’s N3C, N3P, N2P, and A16 nodes, with Synopsys EDA flows and Ansys tools certified for power integrity, electromigration, and electromagnetic extraction. Synopsys.ai, validated on N2P and A16 with NanoFlex architecture, supports scaling and power distribution on the A16 Super Power Rail process. IC Validator certification also ensures full-path ESD verification, helping strengthen design reliability. By extending certification to the latest nodes, the partnership provides customers consistent signoff flows and proven methods.
Multi-Die and 3DIC Enablement
Synopsys’ 3DIC Compiler platform, certified for TSMC’s SoIC and CoWoS packaging, automates routing, TSV and bump planning, and multi-die signoff verification. Several customer tape-outs have already been completed, showing the maturity of these solutions. Certified multiphysics analysis flows, such as thermal-aware and voltage-aware timing, help speed convergence in large 3DIC designs. With AI-driven photonics optimization included, multi-die designs can reach higher performance while meeting thermal and multi-wavelength needs. This integrated support helps customers adopt next-generation 3DIC systems.
Broad IP Portfolio for Next-Generation Standards
Synopsys also provides a wide IP portfolio optimized for TSMC’s advanced processes, covering HBM4, PCIe 7.0, UCIe, 1.6T Ethernet, and UALink. Automotive-focused IP for N5A and N3A nodes, along with SRAM and Foundation IP for 5nm and 3nm SoCs, expand Synopsys’ reach in automotive, IoT, and HPC markets. These offerings reduce integration risk and help speed up silicon development. By combining certified flows, 3D-enabled IP, and photonics design, Synopsys strengthens its role in enabling advanced multi-die and AI designs.
What to Watch:
- The adoption pace of AI-driven design workflows compared to engineer-led approaches.
- Customer traction for certified flows on A16 and N2P nodes.
- Scalability of AI-optimized photonic flows in large 3DIC designs.
- Uptake of Synopsys IP for next-generation standards such as HBM4 and PCIe 7.0.
- TSMC’s progress in addressing energy efficiency challenges in AI chips.
See the complete press release on Synopsys’ collaboration with TSMC to enable 2D and 3D design solutions and the complete press release on Synopsys’ collaboration with TSMC to drive the next wave of AI and multi-die innovation on the Synopsys website.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.
Other insights from Futurum:
Ansys and Synopsys Expand Simulation Capabilities with NVIDIA Omniverse Integration
Synopsys Demonstrates PCIe 6.x Interoperability With Broadcom at PCI-SIG DevCon 2025
Author Information
Ray Wang is the Research Director for Semiconductors, Supply Chain, and Emerging Technology at Futurum. His coverage focuses on the global semiconductor industry and frontier technologies. He also advises clients on global compute distribution, deployment, and supply chain. In addition to his main coverage and expertise, Wang also specializes in global technology policy, supply chain dynamics, and U.S.-China relations.
He has been quoted or interviewed regularly by leading media outlets across the globe, including CNBC, CNN, MarketWatch, Nikkei Asia, South China Morning Post, Business Insider, Science, Al Jazeera, Fast Company, and TaiwanPlus.
Prior to joining Futurum, Wang worked as an independent semiconductor and technology analyst, advising technology firms and institutional investors on industry development, regulations, and geopolitics. He also held positions at leading consulting firms and think tanks in Washington, D.C., including DGA–Albright Stonebridge Group, the Center for Strategic and International Studies (CSIS), and the Carnegie Endowment for International Peace.
