Axelera AI unveiled Titania, a chiplet that runs FP8 and FP4 math inside its digital in-memory compute arrays and wraps every matrix engine in RISC-V cores. Axelera says an 8-package, 4U air-cooled server delivers 20 PFLOPS of FP8 and 1 TB of LPDDR6 at about 6 kW with $300 million in commitments ahead of Q3 2027 production.
What Is Covered in This Article:
- Titania chiplet, package, and AX8 reference server specs
- Third-generation D-IMC macro with native floating point
- RISC-V orchestration and vector cores inside every AI core
- LPDDR6 in place of HBM for MoE decode
- Air-cooled rack density against B200, MI355X, Intel GPU D270, and Qualcomm AI200
- Futurum projections for HBM cost share and accelerator power
The News: Axelera AI unveiled the architecture of Titania, its third-generation inference silicon, on November 12 ahead of SC26 in Chicago. Each Titania chiplet integrates 32 AI cores, 16 compute cores, and 128 MB of cluster-shared SRAM on TSMC N4C, for 1.25 PFLOPS of peak FP8 compute. Two chiplets connect over UCIe in a 400W system-in-package (SiP) with 2.5 PFLOPS of FP8, 16 LPDDR6 modules configurable from 128 GB to 2 TB, 2,458 GB/s of memory bandwidth, 1.28 TB/s of scale-up bandwidth, and a PCIe Gen6 x16 host link. The AX8 reference server places 8 SiPs in a 4U air-cooled chassis.
Axelera says one AX8 server holds a 1.6 trillion parameter model at FP4 with room for KV cache, two fit in a legacy 15 kW rack, and five fit in a 30 kW air-cooled rack. The company projects up to 7x throughput per watt and up to 20x better TCO than the best data center servers available, based on its own simulations. Titania ships as PCIe cards and as OCP UBB baseboards with 8 OAM modules, in air-cooled and liquid-cooled versions through OEM partners. Production begins in Q3 2027 against more than $300 million in confirmed commitments, and the Titania PCIe card is a drop-in replacement for the Europa-based Axelera Server 250p.
“We don’t ask anyone to trust a simulator,” said Evangelos Eleftheriou, CTO and co-founder of Axelera AI. “The architecture behind Titania already turns 88 percent of its memory bandwidth into tokens on Europa silicon that is shipping today.”
Axelera Titania Brings Native FP8 and FP4 to In-Memory Compute
Analyst Take: Axelera Titania is the first time Axelera’s digital in-memory compute (D-IMC) has done floating-point math, allowing an edge architecture to compete for frontier-scale inference. Europa, the shipping second generation, cast floating-point models into INT8 weights and INT16 activations. Titania’s third-generation macro computes MXFP4, FP4, MXFP8, FP8, and BF16 natively inside the SRAM arrays, which are the formats open-weight MoE models now ship in. RISC-V cores surround every array and make each AI core a programmable tile that can run a full network alone. Axelera wraps both in LPDDR6 and a power envelope that fits racks enterprises already own. Futurum views Titania as the most credible D-IMC design yet aimed at data center inference. The proof still sits in simulations of a chip that has not taped out, set against GPU data from September 2026 for a product that reaches volume in 2028.
A Floating-Point Macro Moves Digital In-Memory Compute Into Frontier Model Formats
In-memory compute has always promised to cut the energy spent shuttling weights between memory and arithmetic units and it has paid for that efficiency in numerical flexibility. Axelera’s first two generations ran integer math, casting floating-point values into INT8 weights and INT16 activations to cope with LLM outliers. The Titania macro is a complete redesign. Each AI core now delivers 39.3 TFLOPS of FP8 inside its D-IMC array, and 32 of them reach 1.25 PFLOPS per chiplet. The implication is that customers can run DeepSeek-R1, Qwen 3.5, and GPT-OSS checkpoints in the FP8 and MXFP4 formats their developers published, skipping the integer requantization step Europa required. d-Matrix, the other D-IMC vendor with data center cards in market, built Corsair around block-scaled integer formats. Axelera now claims native floating point across the format range GPU vendors support. Every throughput figure Axelera published for Titania depends on that macro behaving in silicon as it does in RTL-calibrated simulation.
RISC-V Turns the Matrix Engine Into a Programmable Inference Tile
Axelera put RISC-V on the control path of every compute block in Titania. Each AI core pairs its D-IMC array with a RISC-V orchestration CPU that steers data paths, a RISC-V vector CPU with an 8,192-bit vector length, a streaming vector processor for activations, and 2 MB of local SRAM. The 16 compute cores each add 2 RISC-V CPUs with 4,096-bit vectors and 4 MB of shared SRAM to move data between accelerators and run video pre- and post-processing. A RISC-V application processor orchestrates the chiplet. By Futurum’s count of the published block diagram, that is roughly 97 RISC-V CPUs per chiplet. Futurum confirmed that the vector extension is Axelera’s proprietary design and that Titania uses no RISC-V matrix extension, since the D-IMC array performs matrix math. Vector lengths at that scale sit far beyond the 512-bit to 1,024-bit vectors common in licensed RISC-V AI cores such as SiFive’s Intelligence line.
The software claim follows from the hardware. Axelera says its Voyager SDK reached compiler generality on Europa, compiling arbitrary PyTorch graphs through its AxeleraScript DSL, with vLLM and Kubernetes integrations that port to Titania unchanged. “We don’t see any CUDA moat at all in inference,” said Manuel Botija, Vice President and Head of Product at Axelera AI. The new floating-point path and the scale-up fabric have no production compiler history yet, and Tenstorrent, the most visible RISC-V AI rival, competes for the same developers with an open source stack.
LPDDR6 Bets That Bandwidth Utilization Beats Peak Bandwidth
Titania gives each package 2.46 TB/s of LPDDR6 bandwidth, against roughly 8 TB/s of HBM3E on a single NVIDIA B200. Axelera’s case rests on utilization. The company measured 83% of achievable DDR bandwidth on a first port of Qwen3-8B at batch size 1 on Europa silicon, rising to 88% after one optimization pass. Eleftheriou told Futurum that Titania’s projections assume the same or higher utilization, calibrated on RTL data before tape-out. The memory choice also sidesteps the fastest-rising line in an accelerator bill of materials. Futurum’s AI Supply Chain Market Model, published November 6, 2026, projects HBM rising from 11.2% of accelerator revenue in 2026 to 16.9% in 2027. Futurum confirmed Axelera will ship near the 128 GB low end of its LPDDR6 range at launch given current DRAM pricing, which still yields 1 TB per server. The challenge is that an 88% figure on an 8B dense model at batch 1 says little about expert routing on a 397B MoE at mid batch, and LPDDR6 supply is itself tightening as Intel and Qualcomm chase the same capacity.
Air-Cooled Density Opens a Brownfield Market the GPU Roadmap Is Leaving
Axelera Titania targets the racks that NVIDIA’s roadmap has outgrown. Axelera cites Uptime Institute survey data showing more than 80% of operators have no rack above 30 kW, while a Vera Rubin rack runs near 200 kW with liquid cooling. Futurum’s model projects critical IT power per accelerator rising from 1.74 kW in 2026 to 2.63 kW in 2028. An AX8 server works out to about 0.75 kW per Titania SiP. In Axelera’s October rack simulation, 8 Titania servers deliver 43,816 tokens per second on DeepSeek-R1 against 26,900 for 3 competing 10U GPU servers in the same air-cooled rack, and 431,425 against 152,234 on GPT-OSS-120B. Axelera’s public charts label rivals only as numbered competitors. In the briefing Q&A, Axelera identified the enterprise comparison as 8 kW to 12 kW servers built on RTX 6000, Instinct MI325X, H100, and H200, and the data center comparison as B200 and MI355X, using InferenceX data from September 2026.
The LPDDR inference field is filling quickly. Intel’s GPU D270, codenamed Crescent Island, pairs up to 480 GB of LPDDR5X with a 350W air-cooled design. Qualcomm’s AI200 puts 768 GB of LPDDR on each card and ships in 160 kW liquid-cooled racks, and its AI250 adds near-memory compute in 2027. NVIDIA answers the enterprise room with RTX PRO 6000 Blackwell servers, which have the software base Titania lacks. Axelera’s edge in this group is compute per watt inside a 400W package, and each rival is racing to ship first. Titania reaches production in Q3 2027 and PCIe availability in 2028, when its benchmarks will face Rubin-generation and Instinct MI400-series parts that did not exist in the September data.
Older-Node Silicon and European Backing Lower the Execution Risk
Titania’s manufacturing choices favor delivery. TSMC N4C is a cost-optimized 4nm-class node, and Futurum’s model shows accelerator units with compute dies on N5/N4 falling from 7.74 million in 2026 to 2.16 million in 2027 as leading accelerators move to N3. Axelera should face less wafer competition than any rival on N3. The EuroHPC Joint Undertaking’s DARE initiative supports Titania’s development and Axelera names European AI factories among its commitments. Axelera also reports more than 600 customers across Metis and Europa. Startups have stalled on second-generation data center silicon before, and Titania’s commitments total $300 million against GPU vendors booking tens of billions per quarter. Until Axelera tapes out and posts measured numbers on a production MoE model, its 7x and 20x claims remain promising projections.
What to Watch:
- Whether Titania tapes out on schedule for Q3 2027 production
- Whether measured Titania silicon matches 88% bandwidth utilization on a large MoE model
- Whether a tier-one OEM announces an AX8-class server at launch
- Whether the floating-point D-IMC macro pushes d-Matrix or other in-memory rivals to native FP formats
- Whether Intel GPU D270 and Qualcomm AI200 win the same air-cooled enterprise deals
The full announcement about Axelera AI’s Titania Architecture is available here.
Sources
- Axelera AI Unveils Titania Architecture, Business Wire
Declaration of generative AI and AI-assisted technologies in the writing process: This content has been generated with the support of artificial intelligence technologies. Due to the fast pace of content creation and the continuous evolution of data and information, The Futurum Group and its analysts strive to ensure the accuracy and factual integrity of the information presented. However, the opinions and interpretations expressed in this content reflect those of the individual author/analyst. The Futurum Group makes no guarantees regarding the completeness, accuracy, or reliability of any information contained herein. Readers are encouraged to verify facts independently and consult relevant sources for further clarification.
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
