IBM, AMD, and Oak Ridge National Laboratory launched a co-design platform for quantum error correction, colocating IBM’s 120-qubit Nighthawk with ORNL’s Umbra system built on AMD Instinct MI355X GPUs and 5th Gen EPYC CPUs. The deployment makes AMD the classical silicon supplier for the DOE’s 2028 fault-tolerance push.
What Is Covered in This Article:
- A co-design platform for quantum error correction launched by IBM, AMD, and ORNL’s Quantum Science Center
- Colocation of IBM’s 120-qubit Nighthawk with the Umbra system running AMD Instinct MI355X GPUs and 5th Gen EPYC CPUs
- AMD’s heterogeneous role spanning EPYC orchestration, Instinct decoding acceleration, Versal adaptive SoC control, and ROCm software
- The DOE Quantum Genesis Mission target of 100 logical qubits running 100,000 hard operations by late 2028
- Competitive positioning against NVIDIA’s NVQLink ecosystem for the classical side of quantum
- Futurum’s $1.5 trillion 2040 quantum TAM forecast and its hybrid both/and view of AI and quantum
The News: IBM, AMD, and the Quantum Science Center at Oak Ridge National Laboratory announced on November 5 a co-design platform for quantum error correction, the first deployment of which colocates IBM quantum computers, including the 120-qubit IBM Quantum Nighthawk, with ORNL’s Umbra high-performance computing system. Umbra runs on AMD Instinct MI355X GPUs and 5th Gen AMD EPYC CPUs. IBM supplies the quantum processors and its Quantum System API, which gives researchers pulse-level access, mid-circuit measurement with real-time action on results, control over signal timing, and access to raw measurement signals. AMD supplies the classical foundation across its portfolio, with EPYC CPUs for orchestration, Instinct GPUs for simulation and decoding acceleration, Versal adaptive SoCs for low-latency control, readout, and decoding, and the ROCm open software stack connecting HPC and AI applications to the hardware.
The platform lets researchers compare error correction methods by the qubits, time, samples, and classical resources each requires, with planned workflows spanning concatenated codes, space-time codes, algorithm-aware decoders, and hardware-aware circuit optimization. ORNL plans to connect the platform to the Oak Ridge Leadership Computing Facility and its Lux supercomputer, which also runs AMD EPYC CPUs and Instinct GPUs. The work supports the U.S. Department of Energy’s Quantum Genesis Mission and its goal of a scientifically relevant quantum computer by 2028.
“This new co-design platform for quantum error correction allows us to evaluate different approaches and determine the architectures, software and workflows that will scale,” said Jay Gambetta, IBM Fellow and Director of IBM Research. “With Umbra, we will now test new ideas, evaluate approaches at scale, and build the foundation for more reliable quantum computers,” said Travis Humble, Director of the Quantum Science Center at ORNL.
AMD Takes the Classical Side of IBM’s Quantum Error Correction Buildout at Oak Ridge
Analyst Take: AMD is applying its HPC execution muscle to quantum, converting the August 2025 IBM partnership into deployed federal infrastructure in under 15 months. Quantum error correction is the gating function for every fault-tolerance roadmap in the industry and it is a classical computing problem. Decoding syndrome data from thousands of physical qubits in real time, training better decoders offline, and orchestrating the hybrid workflows that stitch quantum processors into scientific computing all run on conventional silicon. Whoever supplies that classical layer collects revenue from the quantum buildout years before any quantum computer pays off.
Futurum’s October 2026 quantum TAM forecast makes the hybrid architecture the destination, with AI proposing candidate molecules and materials, quantum validating them, GPUs decoding error correction in real time, and quantum results becoming the training data AI in science has lacked, as laid out in Quantum Computing Will Break AI’s Science Barrier and Open a $1.5 Trillion Addressable Market by 2040. NVIDIA built NVQLink to claim the classical host position in that hybrid stack. The Oak Ridge platform is AMD’s counter, and it arrives with an advantage NVIDIA has not yet matched, a 120-qubit utility-scale processor physically colocated with a national laboratory’s GPU system and wired for pulse-level experimentation rather than demonstration workloads.
The Genesis Mission Turns Error Correction Into a Measurable Race
The DOE’s Quantum Genesis Mission gives this platform a scoreboard. Through its recently announced Q Competition, the mission targets 100 logical qubits running 100,000 hard operations by late 2028. IBM’s current experiments reach up to 70 logical qubits and 438 hard operations on its Quantum Advantage Tracker, which means the hard operation count must grow roughly 230-fold in two years. That gap is not closed by better qubits alone. Error-corrected operations consume classical decode cycles at rates that scale with code distance and circuit depth, and a decoder that falls behind the quantum processor’s clock corrupts the computation it was protecting. The implication is that the 2028 target is as much a classical systems deadline as a quantum one, and the co-design platform exists to find out which decoder architectures, running on which silicon, keep pace.
Jay Gambetta’s framing that the question is no longer whether error correction works on quantum hardware is supported by IBM’s published demonstrations, though the leap from 438 hard operations to 100,000 remains a thesis the platform must still prove out. The dollar stakes of that schedule are on the record. Futurum projects the quantum TAM will reach $1.5 trillion a year by 2040 in the base case, about $2.1 trillion if error correction arrives around 2027 to 2028, and about $620 billion if it slips to 2033, per the October 2026 Quantum TAM Forecast. A platform built to compress the error correction timeline is working on the single variable that swings Futurum’s 2040 forecast by nearly $1.5 trillion.
AMD’s Portfolio Breadth Matches the Latency Hierarchy of Decoding
The technical fit is the strongest part of AMD’s position. Quantum error correction imposes a latency hierarchy. Qubit control and readout demand sub-microsecond response, real-time decoding runs on a microseconds budget, decoder training and circuit simulation tolerate batch processing, and workflow orchestration sits above all of it. AMD is the only vendor that addresses each tier with owned silicon. Versal adaptive SoCs, inherited from the Xilinx acquisition, handle the control and readout layer where FPGAs already dominate quantum labs. Instinct GPUs take the simulation and decoder-training tier, where IBM already uses AMD GPUs to accelerate the classical diagonalization step in sample-based quantum diagonalization. EPYC handles orchestration. The two companies demonstrated error decoding on AMD chips in 2025, so the Oak Ridge deployment moves a lab result into a production research environment.
NVIDIA’s answer concentrates on the GPU tier, where its lead is sturdy. The October JUPITER run with Jülich simulated a 104-qubit fault-tolerant protocol on 8,192 GH200 superchips, a scale of simulation AMD has not publicly matched, as Futurum covered in NVIDIA’s 104-Qubit JUPITER Simulation Makes GPU Supercomputers the Design Platform for Fault-Tolerant Quantum. The contest is now between NVIDIA’s simulation depth and AMD’s integration breadth. Error correction at production cadence rewards breadth because the decode loop runs on FPGAs and CPUs, where NVIDIA fields partnerships rather than products.
Federal Quantum Infrastructure Is Consolidating Around AMD Silicon
Oak Ridge is becoming an AMD franchise and quantum is the newest tenant. The laboratory’s Frontier system established AMD’s exascale credentials, the roughly $1 billion October 2025 agreement with the DOE put AMD silicon in the upcoming Lux and Discovery systems, and Umbra now extends that footprint into quantum research. Connecting the error correction platform to the Oak Ridge Leadership Computing Facility means IBM’s quantum roadmap will mature inside an AMD-powered computing environment, with obvious pull-through as the work scales toward IBM Quantum Starling, the fault-tolerant system IBM has mapped for 2029 on a path Futurum covered in IBM Maps a $10 Billion Path to Fault-Tolerant Quantum Computing.
Classical control and decode infrastructure sits in the path of federal quantum funding before any of it reaches a dilution refrigerator. The risks are that IBM designs its own control electronics and could internalize more of the classical stack as Starling matures, the platform’s output is research rather than procurement, and NVIDIA’s NVQLink ecosystem spans more than a dozen quantum hardware vendors while AMD’s announced quantum wins concentrate in a single partner. AMD’s quantum position today is deep rather than wide, and the Oak Ridge platform needs to produce published decode results that other quantum vendors want before it becomes a market rather than a partnership.
What to Watch:
- Whether the platform publishes real-time decode latency and accuracy results on Umbra within 2 quarters
- Whether IBM’s Quantum Advantage Tracker shows hard operation counts climbing from 438 toward the 100,000 Q Competition target
- Whether Versal adaptive SoCs appear in IBM’s Starling control stack disclosures
- Whether NVIDIA announces a comparable QPU colocation at a U.S. national laboratory
- Whether additional quantum hardware vendors join the ORNL co-design platform beyond IBM
More details about this announcement are available on IBM’s website.
Sources
- Oak Ridge National Lab, IBM, and AMD Launch New Co-Design Platform for Quantum Error Correction, IBM
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
