At the OCP Global Summit, Texas Instruments introduced the ADC34DSO75, the first analog-to-digital converter to enable 24/7, event-based remote power monitoring at nanosecond resolution, alongside the LMI800PS 800V isolated hot-swap controller and the LMK6B BAW oscillator. The portfolio signals TI’s shift from component supplier to platform provider for AI data center power, monitoring, and timing.
What Is Covered in This Article:
- TI’s ADC34DSO75, the first 3 GSPS ADC enabling 24/7 event-based remote power-rail telemetry at nanosecond resolution
- The LMI800PS 800V isolated hot-swap controller designed against the OCP Diablo 400 specification
- The LMK6B BAW oscillator with 9.6 fs jitter at 625 MHz for 3.2 Tbps networking
- TI’s transition from selling discrete chips to delivering complete modules and reference solutions
- Competitive positioning against Analog Devices, Infineon, onsemi, and SiTime in AI data center analog
The News: At the Open Compute Project (OCP) Global Summit in San Jose, Texas Instruments (NASDAQ: TXN) debuted the ADC34DSO75, which the company describes as the industry’s first analog-to-digital converter to enable 24/7, low-power, event-based remote monitoring of data center power rails at nanosecond resolution. The 3 gigasamples per second (GSPS) device combines high-speed sampling with on-chip digital signal processing and memory to capture transient power faults that TI states are thousands of times faster than current power monitors can detect. TI also announced the LMI800PS, the industry’s first 800V isolated hot-swap controller, which replaces a five-IC discrete solution with a single package, reduces board area by more than 60%, and supports both ±400V and 800V distributions, and the LMK6B, a bulk acoustic wave (BAW) oscillator delivering 9.6 femtoseconds of jitter at 625 MHz for data center networking approaching 3.2 Tbps. Preproduction quantities of all three devices are available on TI.com.
TI Debuts Nanosecond Power Telemetry at OCP to Cut AI Data Center Downtime
Analyst Take: TI’s OCP Global Summit announcements establish nanosecond power telemetry as a new product category in AI data center monitoring. The ADC34DSO75 addresses a failure mode that current infrastructure cannot see: AI training and inference workloads swing power consumption on a cycle-by-cycle basis, and the resulting power rail glitches cause brownouts that take racks or models offline. In our analyst briefing, TI executives stated that existing power rail monitors sample at tens to hundreds of kilosamples per second because they were designed for steady DC telemetry within power factor correction systems. A 3 GSPS converter with event-based capture increases monitoring resolution by four orders of magnitude, giving hyperscalers their first practical tool for correlating transient electrical behavior with GPU reliability degradation. TI framed the capability as an oscilloscope at each node without the oscilloscope, a claim that preproduction availability now allows customers to test.
Event-Based Intelligence Differentiates the Platform From Faster Sampling Alone
The device’s differentiation rests on architecture rather than raw speed. Programmable thresholds inside the ADC detect high or low voltage excursions and rate-of-change violations within a time window, then write the surrounding samples to an on-die memory buffer that offloads through a low-cost MCU rather than an FPGA. Karthik Vasanth, Vice President and General Manager of TI’s Data, Converters and Clocks business unit, described the module-level design in the briefing as including a second off-chip memory that acts as a black box, preserving the milliseconds before a catastrophic event for post-mortem analysis. The module packages two four-channel ADCs with amplifiers for direct connection to CPU and GPU power rails, and channels daisy-chain to scale across additional rails without proportional IO cost. The rail placement is agnostic and hyperscalers choose which contentious rails to instrument, while slower PSU-level telemetry persists alongside. This is a system design philosophy that turns a converter spec sheet into an operational reliability tool and explains why TI is selling modules rather than chips. Vasanth was explicit that TI is repositioning around complete solutions spanning hardware and software because customers lack the time to evaluate individual parts, a notable strategic admission from a company built on a 80,000-SKU catalog model.
OCP Standards Alignment Converts Analog Content Into Platform Design Wins
The portfolio is engineered to the specifications that OCP and NVIDIA are driving into next-generation racks. The LMI800PS was designed against the OCP Diablo 400 specification rather than generic high-voltage requirements, placing the hot-swap controller directly inside the 800VDC architecture NVIDIA outlined for AI factories and the Mt. Diablo power rack work OCP members are standardizing. The device’s support for both ±400V and 800V distributions covers the two competing DC distribution schemes while the market settles, and its 5kVrms reinforced isolation with more than 8mm of creepage addresses the safety problem of placing high-voltage DC on boards dense with low-voltage processors.
Designing to the OCP specification allows hyperscaler rack programs to qualify components against these documents and shorten qualification cycles in a market where, as Vasanth noted, customers no longer have time to evaluate parts individually. The LMK6B plays the same standards game in timing, specifying jitter performance a factor of five to ten below SerDes requirements so that clocking drops out of the signal-integrity budget as lanes move toward 3.2 Tbps and more complex PAM signaling. Futurum notes that TI’s BAW technology is silicon-process compatible, giving TI a manufacturing cost argument against quartz incumbents and MEMS specialist SiTime.
The Platform Pivot Carries Execution Risk Against Entrenched Analog Rivals
The bear case is that TI is creating a category before demand is proven. It remains unclear whether power glitches are occurring more frequently or were simply invisible before, only that hyperscalers report rising concern. The thousands-of-times-faster claim is measured against kilosample-class PFC telemetry and remains a vendor benchmark until hyperscalers publish correlation data linking nanosecond events to downtime avoided. Adoption will start with hyperscalers at the GPU rail and must percolate to server OEMs for volume, a path TI itself described as just beginning.
Meanwhile, the competitive field is converging on the same opportunity. Analog Devices reported AI-linked data center and power demand as a growth driver and holds strong positions in precision monitoring and isolation, Infineon and onsemi are anchoring the 800VDC power chain from the grid side, and Vicor and Delta dominate high-density conversion stages. None has yet shipped an event-based nanosecond telemetry converter, which gives TI a window measured in product cycles rather than years. TI’s data center revenue momentum, up on broad-based analog growth in Q2 FY 2026, suggests the company is converting its foundational technology positioning into revenue ahead of the 800V transition rather than waiting for it.
What to Watch:
- Whether hyperscalers publish reliability data correlating nanosecond power events with GPU failures, validating the monitoring category TI is creating
- Whether the ADC34DSO75 wins design-ins at the GPU power rail or hyperscalers confine it to debug deployments
- Whether OCP ratifies telemetry requirements in Diablo-family specifications that would make nanosecond monitoring a qualification checkbox
- Whether ADI, Microchip, or Renesas responds with event-based telemetry converters within the next two product cycles
- Whether TI’s module and complete-solution model gains traction with server OEMs beyond the initial hyperscaler engagements
See the complete press release on the TI newsroom.
Sources
- TI unveils new ADC to enable nanosecond-level telemetry and minimize downtime in AI data centers, TI, October 2026
Declaration of generative AI and AI-assisted technologies in the writing process: This content has been generated with the support of artificial intelligence technologies. Due to the fast pace of content creation and the continuous evolution of data and information, The Futurum Group and its analysts strive to ensure the accuracy and factual integrity of the information presented. However, the opinions and interpretations expressed in this content reflect those of the individual author/analyst. The Futurum Group makes no guarantees regarding the completeness, accuracy, or reliability of any information contained herein. Readers are encouraged to verify facts independently and consult relevant sources for further clarification.
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
