Lattice Semiconductor announced a collaboration with Arm on October 7 that places Lattice FPGAs and AMI platform firmware inside Arm AGI CPU server platforms for secure control, management, and platform adaptability. The companies will demonstrate a joint server at OCP Global Summit 2026. Futurum reads the attach as Lattice securing the control socket in the first merchant Arm server platform before its deployment wave builds.
What Is Covered in This Article:
- Lattice-Arm collaboration placing Lattice FPGAs beside the CPU and BMC in Arm AGI CPU server platforms
- AMI firmware supplying platform boot and management on the joint design
- OCP-compliant HPM to DC-SCM connectivity through the open LTPI interface
- Joint server demonstrations at OCP Global Summit 2026
- Competitive mapping across Microchip, AMD, Altera, ASPEED, Nuvoton, Axiado, and hyperscaler in-house control silicon
The News: Lattice Semiconductor (NASDAQ: LSCC) announced a collaboration with Arm on October 7 to enable secure control, management, and platform adaptability for AI infrastructure. In Arm AGI CPU server platforms, Lattice FPGAs operate alongside the CPU and the baseboard management controller as companion chips for platform trust, connectivity, and infrastructure adaptability, while AMI firmware provides platform boot and management. Lattice FPGA technology also enables Open Compute Project (OCP)-compliant connectivity between the Host Processor Module (HPM) and the Datacenter Secure Control Module (DC-SCM) through the LVDS Tunneling Protocol and Interface (LTPI), an open, standardized interface for modular platform integration. The joint Arm and Lattice server will be showcased at OCP Global Summit 2026, featuring an Arm AGI CPU-based platform with Lattice FPGAs for secure management and control.
“By working with Lattice to integrate secure management and control, we’re expanding the ecosystem around Arm AGI CPU and giving customers more flexibility to build and deploy next-generation AI infrastructure,” said Eddie Ramirez, Vice President of Go-to-Market, Cloud AI, Arm.
“Together with Arm, we’re helping customers accelerate deployment of next-generation computing platforms through secure management, open standards, and a scalable foundation that can evolve with changing customer needs,” said Mamta Gupta, VP, Business Development, Compute & Communications, Lattice Semiconductor.
Lattice Brings FPGAs and AMI Firmware to Arm’s $15 Billion AGI CPU Server Push
Analyst Take: Lattice is becoming the control standard of Arm’s open server ecosystem. Arm AGI CPU is the first finished server processor Arm has sold under its own name, with Meta as co-design partner and OpenAI, Cloudflare, SAP, and SK Telecom among early customers. Arm built the platform on open OCP standards to pull an ecosystem around it, and that choice routes buyers toward Lattice, which wrote the LTPI modularity protocol into the OCP DC-SCM specification, ships the companion FPGAs that implement it, and now supplies the AMI firmware that boots and manages the platform. The more open Arm makes AGI CPU, the more of its control plane will run on Lattice-defined technology.
Every AGI CPU server that ships needs a root of trust, power sequencing, telemetry, and board-level management logic. Arm has attached numbers to the opportunity: management targets roughly $15 billion in annual AGI CPU revenue by fiscal 2031, with a near-term goal of about $1 billion across fiscal 2027 and 2028 and customer demand visibility Arm placed at $2 billion on its most recent earnings call, where executives described shipments as supply-capped. Lattice’s control content will scale with the high-growth agent CPU product category.
Merchant Arm Silicon Gives the Companion FPGA a Standard Socket
Arm’s shift from IP licensor to silicon vendor changes the economics of attaching to Arm servers. When every Arm server CPU was a custom hyperscaler design, from Graviton to Axion to Cobalt, the control plane around each one was also custom, and a companion chip vendor had to win each board individually. AGI CPU creates a merchant platform with an OCP DC-MHS reference server, published specifications, and a roster of system builders including Lenovo, Supermicro, ASRock Rack, and Quanta, so a reference control plane design can propagate across every OEM implementation at once.
The platform’s density pitch raises the stakes for management silicon. Arm’s reference design packs up to 8,160 cores into a 36kW air-cooled rack and claims more than 2x the performance per rack of comparable x86 deployments, a figure pending initial benchmarks. Denser racks multiply the sequencing, telemetry, and security logic each tray requires, which is the demand function Lattice’s control FPGAs serve. Lattice has positioned its content where the CPU market’s fastest structural shift is occurring rather than defending sockets in the slower x86 refresh cycle.
LTPI and AMI Firmware Convert a Chip Sale Into a Platform Standard
The technical substance of the announcement sits in the interface and the firmware rather than in any new device. LTPI tunnels the many low-speed signals between the host processor module and the DC-SCM over a single LVDS link, which is the mechanism that lets one management module design serve multiple motherboard generations. Lattice authored the protocol into the OCP DC-SCM specification and ships it across its control FPGA families, so an AGI CPU platform built on LTPI inherits a Lattice-defined interconnect as its modularity layer. AMI compounds the position. The $1.65 billion acquisition, closed in July, gave Lattice the Aptio BIOS, MegaRAC BMC firmware, and Tektagon platform root-of-trust software that already run across AWS, Google, Microsoft, Meta, Dell, and Supermicro systems. This announcement is the first vendor platform design win that bundles the firmware with the silicon since the deal closed.
A buyer evaluating an AGI CPU server from any OEM can now expect boot, management, and attestation from one supplier that remains silicon-neutral across the XPUs in the same rack. The combination also fits the buying pattern Futurum identified in its AMI acquisition coverage, where control-plane decisions increasingly shape platform design wins before compute selection is final. The Mach-N2 family announced in September extends the offer into post-quantum territory, with full CNSA 2.0-compliant cryptography that will become a US federal procurement gate on January 1, 2027, although the Arm announcement does not specify which Lattice device families are included in the joint design.
The Control Socket Is Contested and AGI CPU Volume Is Unproven
Commercial challenges will come in two parts. The first is competitive. Microchip sells PolarFire-based control solutions with its own root-of-trust claims, AMD and Altera field small FPGAs for the same sequencing and glue roles, ASPEED and Nuvoton dominate the BMC silicon that sits beside the Lattice part on every DC-SCM, and Axiado is pitching an integrated trusted control unit that would collapse the BMC, root of trust, and control FPGA into one device. Hyperscalers add a structural threat, since Google’s Titan and Microsoft’s Cerberus lineage show the largest buyers will design their own platform security when it suits them, and OCP’s Caliptra project is standardizing an open root-of-trust block that any silicon vendor can embed, which over time could migrate functions off the companion FPGA and into the CPU or BMC package itself.
The second part is demand. AGI CPU carries named customers and system partners, yet neither Arm nor Lattice has disclosed shipment volumes, and Meta’s co-design role suggests the largest early deployer may customize its control plane rather than adopt the reference design wholesale. The announcement also contains no revenue terms, no exclusivity, and no content-per-server figure, so the financial weight of the attach cannot be sized yet. Futurum’s view is that the default outcome is layered coexistence, where Lattice supplies the reference design and merchant OEM volume while the largest hyperscalers blend in-house security blocks with Lattice connectivity parts. The signal that would indicate a stronger outcome is a hyperscaler AGI CPU deployment publicly naming the Lattice and AMI stack.
What to Watch:
- Whether OCP Global Summit demos identify the specific Lattice FPGA families, including Mach-N2, in the joint AGI CPU platform
- Whether Meta’s AGI CPU deployments adopt the Lattice and AMI reference control plane or substitute in-house security silicon
- Whether Lenovo, Supermicro, ASRock Rack, and Quanta AGI CPU systems ship with Lattice control FPGAs and AMI firmware
- Whether Caliptra-based root-of-trust integration begins displacing discrete control FPGA functions in OCP server designs
Read the complete announcement in the Lattice newsroom.
Sources
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure, Lattice Semiconductor
Declaration of generative AI and AI-assisted technologies in the writing process: This content has been generated with the support of artificial intelligence technologies. Due to the fast pace of content creation and the continuous evolution of data and information, The Futurum Group and its analysts strive to ensure the accuracy and factual integrity of the information presented. However, the opinions and interpretations expressed in this content reflect those of the individual author/analyst. The Futurum Group makes no guarantees regarding the completeness, accuracy, or reliability of any information contained herein. Readers are encouraged to verify facts independently and consult relevant sources for further clarification.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
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Other Insights From Futurum:
Lattice Mach-N2 Turns the Post-Quantum Procurement Gate Into an FPGA Moat
Lattice Semiconductor Q2 FY 2026: AMI Acquisition Pulls $1 Billion Revenue Rate Up to Q3 2026
Lattice Semiconductor Q1 FY 2026 Results Set Up AMI Acquisition
Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
