ASML reported that Intel Foundry has entered high-volume manufacturing on select Intel 18A layers using High-NA EUV, producing a subset of Panther Lake processors at yields matched to the incumbent 0.33NA platform. The milestone puts Intel years ahead of its foundry rivals on the lithography ladder that will define the Angstrom era.
What Is Covered in This Article:
- ASML confirmed Intel Foundry is the first company to ship high-volume logic patterned with High-NA (0.55NA) EUV, using dual-qualified Intel 18A layers for a subset of Panther Lake Intel Core Ultra Series 3.
- How the Intel Foundry High-NA EUV milestone builds a production learning curve that competitors will need years and volume to replicate, aided by a High-NA ramp proving smoother than the original EUV introduction.
- Why the capability aligns with Intel’s long-stated plan to run High-NA on 14A and positions Intel to industrialize the next architectural steps, from ASML’s Hyper-NA roadmap to IBM’s nanostack transistors.
The News: ASML reported on July 15, 2026 that Intel Foundry has entered high-volume manufacturing on select Intel 18A layers using ASML’s EXE High-NA EUV platform, producing a subset of the Intel Core Ultra Series 3 processors code-named Panther Lake. Specific 18A layers are now dual-qualified on High-NA EUV at Intel’s Oregon site, with product shipping to customers at yields ASML says are matched to those of the incumbent 0.33NA NXE platform.
The milestone makes Intel Foundry the first company in the industry to ship a high-volume logic product patterned with High-NA EUV, roughly two years after it integrated the world’s first commercial TWINSCAN EXE:5000 system at Hillsboro in 2024 and became the first to install and accept the second-generation EXE:5200B.
“This milestone reflects the close technical collaboration between Intel and ASML and shows how High-NA EUV can be integrated into advanced semiconductor manufacturing at scale,” said Naga Chandrasekaran, Executive Vice President and General Manager of Intel Foundry.
Will Intel Foundry’s High-NA EUV Lead Compound Into a 14A Advantage?
Analyst Take: Running High-NA EUV in a revenue-bearing production line is the milestone the leading edge has been waiting for at a time when the AI compute build-out has made transistor density and power efficiency the currency that decides who wins the market. Matching NXE-platform yields on dual-qualified 18A layers is the proof point that production-grade yields, the hardest part of a lithography transition, will be achieved, creating optionality for customers at the upcoming 14A node. Intel will start building High-NA manufacturing know-how while TSMC and Samsung remain in the planning phase, and the gap should widen with volume. That may become a genuine competitive advantage as TSMC defers usage of the technology until after its A14 process.
The Production Head Start Is the Advantage Competitors Cannot Buy
High-NA hardware is available to any foundry willing to commit roughly $350 million per scanner and a fab slot. The durable advantage lies in the knowledge of how to run the tool at volume, including field stitching and a slower dosing process to manage defects. Intel has been building that knowledge base since 2024. High-NA can compress EUV’s timeline because it inherits the mature EUV ecosystem including the same light source, mask infrastructure, resist platforms, and computational lithography. As a result, going first on High-NA carries far less ramp risk than going first on EUV did. By dual-qualifying 18A layers and shipping them to customers, Intel turns two years of R&D into a manufacturing advantage.
TSMC has made the opposite bet by staying on 0.33NA EUV with advanced multi-patterning, only beginning to install High-NA evaluation tools in early 2026. At TSMC’s volume, the roughly 2.5x cost-per-exposure premium of a High-NA tool does not yet beat pushing depreciated 0.33NA scanners through multi-patterning, but it leaves Intel accumulating a production learning curve that its largest rival is deliberately deferring by two years or more, an edge that pays off if High-NA economics mature on the faster trajectory Intel’s own ramp is now demonstrating.
High-NA Capability Creates Optionality for 14A and Beyond
High-NA on 18A is a stage in a roadmap Intel has pointed to for years. Intel has positioned 14A as the industry’s first node to use High-NA in high-volume logic, pairing it with RibbonFET and backside power delivery, with the 0.9 PDK reaching external customers in October 2026, risk production in 2028, and high-volume manufacturing in 2029. Intel has also said it will build 14A capacity only against firm external commitments due in the 2026–2027 window, which makes today’s 18A proof point the credential it needs to land them.
Beyond 14A sits Hyper-NA. At SPIE Advanced Lithography 2026, ASML EVP of technology Jos Benschop presented a 0.75 NA system as “a natural next step,” framed as printing features roughly 36% smaller, near 5 nm, for 1 nm-class nodes in the early 2030s. Those are ASML roadmap targets rather than demonstrated results, but the disciplines they demand — source stability, overlay control at high numerical aperture, and stochastics management — are the same ones Intel is mastering now, so its first-mover position on 18A compounds up the entire ladder.
High-NA Positions Intel to Industrialize IBM’s Nanostack the Way It Did Nanosheet
Intel’s High-NA lead positions it to commercialize the next device architecture as it did the last one. IBM invented gate-all-around nanosheet but captured little of the value after exiting manufacturing in 2015. The economics flowed to the foundries that built fabs around it, including Intel with RibbonFET. IBM’s June 2026 nanostack breakthrough sets up the same dynamic, and its hard problems are process problems including wafer bonding, an ultra-thin defect-free dielectric, and 3D metrology that still must be patterned at leading-edge density. IBM acknowledges that High-NA EUV will be advantageous for the design, and the single-exposure patterning Intel is already proving on 18A, paired with backside power delivery, give it the integration toolkit to turn IBM’s research device into a manufacturable node first.
What to Watch:
- Whether Intel converts external 14A commitments in the 2026–2027 window to fund High-NA buildout
- Whether High-NA layers exceed NXE yields
- Whether TSMC and Samsung accelerate their testing to catch up
- Whether Intel moves to industrialize IBM-style nanostack transistors, the architectures where its High-NA experience transfers.
See the full press release on ASML’s website.
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
