Intel Foundry has moved Intel 18A-P, the first performance enhancement to its 18A node, into risk production, delivering 9% higher performance or 18% lower power along with a new Power Boost transistor. The update reinforces Intel’s industry lead in pairing gate-all-around transistors with backside power delivery. With full design-rule compatibility, on-schedule delivery, and a compelling PPA story, Intel 18A-P positions Intel Foundry to enable external customers to adopt the process and commit design starts on a leading-edge node backed by a credible long-term roadmap.
What Is Covered in This Article:
- Intel 18A-P, the first performance enhancement in the Intel 18A family, has entered risk production on schedule, running lead products in Intel’s Oregon and Arizona fabs.
- The node delivers 9% higher performance at iso-power or 18% lower power at iso-performance versus Intel 18A, while remaining fully design-rule compatible with Intel 18A.
- A new “Power Boost” dual-contact transistor, enabled by PowerVia backside power, raises drive current and frequency at matched capacitance without adding cell area.
- Intel quantified its gate-all-around plus backside power delivery advantages and previewed long-range research in CFET, GaN-on-silicon, and ruthenium interconnects.
- The critical unlock for customer design wins: Intel’s process-technology lead in combining backside power with gate-all-around is real, but converting it into foundry customer traction and closing the yield gap is the decisive test.
The News: At the 2026 VLSI Symposium, Intel Foundry announced that Intel 18A-P has entered risk production, meeting the timeline first shared with customers and partners a year ago. Intel 18A-P delivers 9% higher performance at iso-power or 18% lower power at iso-performance compared with Intel 18A, achieved through a mix of transistor, interconnect, and design-technology co-optimizations. These include a new dual-contact “Power Boost” device, 20–40% improved thermal resistance, 10–30% improved via resistance at performance-critical layers, a mobility enhancement via PMOS strain engineering, new low-power and high-performance transistor options, and a new fifth logic Vt pair between ULVT and LVT. The node is fully design-rule compatible with Intel 18A, enabling straightforward reuse of existing IP and design flows.
“Our updates and presentations at VLSI signal to Intel Foundry customers and partners that we are fully committed to leading edge process innovation over the long term,” said Naga Chandrasekaran, executive vice president and general manager of Intel Foundry. “This is a journey, and while we have more work ahead, we appreciate the opportunity to share the progress we are making with Intel 18A-P and our longer-range R&D.”
Will Intel 18A-P Risk Production Bring External Foundry Customers Through the Door?
Analyst Take: Intel 18A-P entering risk production is, on its surface, a narrow engineering update: the first performance enhancement to a node that is already shipping in laptops. More precisely, it is the clearest evidence yet that Intel Foundry can do the one thing it has struggled to do for a decade — say what it will deliver, and then deliver it on schedule. The Intel 18A-P milestone lands exactly when Intel told customers it would last year, with lead products already running in both Oregon and Arizona. For a foundry whose single biggest credibility gap has been predictable execution, hitting the date matters at least as much as the 9% performance number attached to it.
Intel 18A-P Turns a Schedule Promise Into a Process Milestone
The headline figures are competitive. Intel 18A-P offers roughly 9% higher performance at constant power, or 18% lower power at constant performance, measured on an industry-standard Arm core across the full voltage range. Intel itself notes that a typical full node delivers 10–15% performance improvement, so a within-family enhancement of nearly 9% is unusually large. The gains come from several stacked improvements rather than one lever: a 20–40% reduction in thermal resistance, a 10–30% improvement in via resistance at performance-critical layers, intrinsic PMOS mobility gains from strain engineering, and a new fifth Vt pair plus new low-power transistor widths that give designers more room to trade speed against power. Crucially, Intel 18A-P is fully design-rule compatible with Intel 18A and matches its reliability, so customers can reuse existing IP and design flows instead of re-spinning their work.
Power Boost and Backside Power Produce a Process Advantage
The most differentiated piece of Intel 18A-P is Power Boost, a second-generation backside-contact transistor. Where Intel 18A connects the transistor through a single frontside contact, Power Boost adds a direct backside contact enabled by PowerVia, effectively opening a second door for current to exit the device. The result is lower resistance, higher drive current, and greater frequency at matched capacitance. Because the backside contact reuses structure that already exists, it adds no cell area. This is the kind of advantage that is hard to copy quickly, and it reinforces Futurum’s standing view that Intel Foundry leads the industry in combining backside power delivery with gate-all-around transistors. Intel reinforced that lead at VLSI with quantified data: an invited talk detailed roughly 11% routed-area reduction, a 10x dynamic voltage droop reduction, and up to 6% frequency uplift or greater than 15% dynamic-power reduction versus comparable frontside interconnect. A separate circuit-level paper showed about 30% frequency improvement at low voltage (~0.5V) on gate-all-around CPU cores. Intel’s decision to build Intel 18A with four transistor ribbons, rather than the three used by Samsung and TSMC, is the design choice underneath much of that drive-current advantage.
The Research Pipeline Signals Longevity, Not Near-Term Revenue
Intel paired the Intel 18A-P news with a long-range research story that is strategically important even if commercially distant. It demonstrated monolithic CFET inverters with vertically stacked NMOS and PMOS at a 45nm gate pitch, 300mm monolithic integration of gallium-nitride power devices with a roughly 1,000-gate silicon control block, and subtractive ruthenium interconnect with airgaps achieving about 35% capacitance reduction versus copper. None of this ships soon, but together it answers the more existential question customers ask before committing multi-year roadmaps to a foundry: is there a credible path beyond gate-all-around and beyond copper? Signaling that depth of pipeline is itself part of rebuilding trust. The bottom line is that Intel 18A-P is exactly the kind of disciplined, on-time delivery Intel Foundry needs to be making — the technology case is increasingly hard to argue with. The open question is whether execution and yield convince external customers to bet their silicon on it.
What to Watch:
- Whether a one-quarter defect-density gap with Intel 18A will close as volume ramps.
- Merchant foundry tape-outs are the metric that validates the turnaround.
- Competitive costs and capacity to TSMC N2, A16, and Arm-based hyperscaler silicon
- Intel’s thermally aware tool flows with Cadence, Synopsys, and Siemens will shape how much of the 18A-P headroom designers can actually use.
- With the substrate effectively removed, Intel 18A-P opens new options for EMIB, Foveros Direct 3D, and memory stacking that could matter more than the transistor gains over the next several years.
See the full announcement on Intel’s website.
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
