The Six Five Insider Edition with Thy Tran, VP of DRAM Process Integration at Micron

The Six Five is live for Micron’s 1-beta DRAM announcement unveiled this week with the company announcing its next DRAM process node, 1-beta, the world’s most advanced DRAM technology.

Hosts Patrick Moorhead and Daniel Newman are joined by Thy Tran, VP of DRAM Process Integration at Micron, for another Six Five “Insider” edition podcast. Their conversation covered:

  • The journey to 1-beta DRAM, including overcoming scaling difficulties
  • How Micron is uniquely leading the marketing in both DRAM & NAND and what they have done to achieve this
  • The benefits 1-beta has for mobile memory, specifically LPDDR5X, which the company is now shipping samples of on the 1-beta node
  • A preview of future benefits the 1-beta process node will bring to end market segments

To learn more about this announcement, check out Micron’s website.

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You can listen to the conversation here:

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Announcer: This week, Micron technology unveiled an exciting step forward for its DRAM innovation and the memory market with the shipping of its one beta DRAM process technology to the mobile ecosystem. It’s 1-beta node, the world’s most advanced DRAM technology cements micron as uniquely leading in both DRAM and NAND Innovations. Daniel Newman and Patrick Moorehead spoke with Thy Tran, Micron’s VP of DRAM process integration to get the inside scoop on all the exciting innovations that went into this major milestone and what this means for the market.

Patrick Moorhead: Hi, this is Pat Moorehead with more insights and strategy and we are here for another six five Insider podcast. I am broadcasting from probably more than an undisclosed location if you can look over my shoulder here on the west coast. But I am joined by my amazing co-host Daniel Newman, founder of Future and Research. Daniel, how are you my friend?

Daniel Newman: Hey Pat. Good morning. It’s beautiful and it looks like our sky is continuous right now, almost the way it’s setting up perfectly. ‘Cause we are both on the west coast and it is good. I’m not where you are and that’s kind of rare because people get used to seeing you and I in the same place. But it’s also one of those cases where we are all over the map right now. So many events, so much travel, but so much to be excited about. But I am really, Patrick, excited about this conversation today. This is going to be a good one.

Patrick Moorhead: Now. Absolutely. So now without further ado, let’s introduce Thy Tran, she’s VP of DRAM process integration from Micron. Thy, happy announcement day. How are you doing?

Thy Tran: I’m doing great, thank you Patrick and Daniel. Thanks for having me.

Patrick Moorhead: Yeah, absolutely. So Danny you want to, let’s jump right in.

Daniel Newman: Yeah, it’s great and I like that we are using it. We’re being a little bit ambiguous right now. It’s announcement day. What does that mean? Well, you know what Thy, we brought you on the show. So what I will say is this, you guys have made some really big progress over the last year. It’s another big announcement 1-beta. Let’s unpack that. What is it, What does it mean for the market?

Thy Tran: Well, it’s incredibly exciting and this 1-beta milestone is a huge one for Micron. It marks the second time that we’re leading the industry in both DRAM and NAND. So we’re conscious, we were conscious about how competitive the landscape is out there for DRAM and we wanted to avoid being the one hit wonder and we wanted to have a steadfast performance and our leadership so that we can maintain our industry leadership in the market.

Patrick Moorhead: Yeah. We’ve been covering your first to market and those never get boring, but I’ll admit, and I mentioned this to you in the green room, Micron was not as communicative as it was for a few years and then I was wondering, hey, what’s going on there? And then you come out this, hey first to market with this in NAND, first in market with DRAM. And the latest one that we had talked about and that I’d written about was your first to market 232 layer NAND. And then here we are one Alpha DRAM 176 layer NAND. So the question is the how, it’s obviously you’re doing it, but can you talk maybe a little bit about your innovations, your investment, in that you’re able to get ahead of the competition like Samsung and Heinex?

Thy Tran: Sure, I wanted to call out that, it’s interesting how you note that we used to be a quieter or more stealth mode and we were very careful to basically avoid announcing things that we cannot deliver. So we wanted to have concrete achievements in hand before we announce, make announcements. So with respect to innovation and how we’re achieving that in both the DRAM and NAND, our executive team have been quite aggressive. And our board also in terms of enable us to invest in not only new tools, new equipment, but also in terms of our engineering and manufacturing facilities, our pathfinding team.

And then also if you look back some years ago we were actually behind the competition, in both DRAM and NAND. And so we search ahead and we led the competition in NAND and then DRAM, we were struggling for quite some time. But along the way we basically, instead of trying to play fast follower, we change our mindset to be trying to lead instead of follow. And we have this new way that we’re working and we innovate and we’re much more aggressive in terms of scoping out what is possible instead of trying to follow the pack.

Daniel Newman: Yeah, I always like quiet and effective in my opinion. Especially right now in this kind of difficult market space. We want to hear from companies that are getting it done. And so as far as we’re concerned, don’t feel bad about being a little stealthy. That’s okay. A lot of companies make a lot of noise, they’re really loud and then what they come out with doesn’t necessarily meet the innovation requirements. So you can kind of go both ways and it seems you’ve picked that latter path, which is great. Talk a little bit more about the specifics of the, and this has got to be your thing. I just based on your title this, we’re getting right into your wheelhouse here. But when it comes to the innovation and the techniques that Micron is using and adding to achieve this 1-beta. So you went from 1-alpha to 1-beta. What did you do to really drive this innovation in the process?

Thy Tran: So basically, we look at all aspects, multiple fronts. We initially scope out whether a process or a module or the entire flow is scalable to the next shrink. So we go about by first starting with the memory array, that’s kind of like the holy grail, how aggressive can you shrink that? And traditionally that was where the focus was. And as we start hitting the scaling wall or starting to hit the limits of physics, we had to look in other ways to be more creative and push the other aspects of the dye. But most of the dye, the chip that you have is taken with the area by the memory cell array and the rest of the circuitry, the sense amplifier, the word driver and the periphery devices, all the core logic and so on. Before it was not keeping pace with the memory cell array shrinked. So through collaboration with our technology team from process integration to process engineering and also design team and product engineering team, we collaborated in a holistic way.

And so we scope out what is possible in terms of not only pushing from the process side, but enabling design and technology co-optimization. So we find the sweet spots for each, and everything is on the table. We don’t just shrink the cell array, we shrink everywhere that’s possible. So we challenge ourselves to be aggressive and make risk decisions by committing to something, betting on something with our engineering judgment, with our fundamental studies. And then pushing beyond what we think is possible in terms of multi-patterning technology as our competitors have forged ahead with EUV lithography. But our strategy has been you deploy it when you really need it and it has to meet the performance of multi patterning strategy and the cross point. And through our engineering prowess, our innovation prowess, we also were able to leverage between NAND and DRAM technology. So we borrowed the initial pitch or we call it pitch multiplication, but you can call it multi-patterning.

And we leveraged that for DRAM and because a capacitor has very stringent, the most stringent requirements in terms of critical dimension uniformities for example. And how we patterned that, we had to also innovate and advance that technique and process. So besides the traditional line space printing, we were able to advance our multi-patterning process for contact layers for different layout configurations. And so additionally, besides the patterning, which is the first step, you got to make the features, we have to meet all of the electrical requirements, for example, resistance capacitance to meet the parasitic requirements, not only in the array but also the rest of the dye.

So besides just focusing on the capacitor and how much capacitance we can get for refresh and still meet the leakage requirements and the other parameters like array timings and whole row hammer type of mode that we have to protect the customers from, we basically have to engineer every single module. Capacitor used to be the most critical module. Now you look everywhere, everything is hitting the limit of the scaling wall. So do you reduce your shrink or do you push the limit? And then you find the sweet point, sweet spots for each of those in terms of process design points and geometry design points. And you integrate that both with technology and design.

Patrick Moorhead: Thy my mind is always blown when we have somebody intelligent and super smart and super experienced on the show. But my net net from that is that you take a device approach, a couple of things. First of all, you take a device approach versus the cell, right? You’re not just looking at the cell and shrinking it, you’re looking at the entire device and ways you can optimize for that. And the other thing you talked about is, Micron has a very robust memory and storage business, so NAND and DRAM and you’re able to leverage many of those learnings particularly on the process technology improvements. And I’ll bet there’s some advantage on the design side to leverage that. So we’ve talked a little bit ethereally at a very Micronic level, get it, but hey, let’s talk about the devices them themselves. So your first launching 1-beta on your mobile memory, LPDDR5X. And I’m curious, what are some of the benefits that you are most excited about with LPDDR5X and the mobile ecosystem?

Thy Tran: So yes, the LDPPR5X, it’s hard to say, which I’m really most excited about because we’re reducing the power by 15% on that front. And from a sustainability standpoint that is always good for our earth. And I would say that the fact that we can hit the four, I would say the three corners, the density, memory, density capacity improvements over 35%, the 15% in power reduction and at top speed of 8.5 gigabits per seconds. And if you look at as a whole that triangle of hitting those three we’re able to achieve our cost point, which is one of the reason why we deployed next-generation DRAM at NAND. So holistically, the technology 1-beta allows us to deploy the broadest product portfolio. So what I think I’m most excited about is not only particularly for DDR5X, but the ability for us to farm that owl to all market segments. And that’s quite powerful. I would say it’s probably the technology, the node that is enabling the broadest product portfolio.

Patrick Moorhead: Yeah. And just a quick clarity question. When you say mobile, is that smartphone or smartphone and notebooks?

Thy Tran: Wait, so mobile, yes, actually is both. But initially the LPDDR5X, we are focused on the smartphone markets.

Patrick Moorhead: Excellent. Yeah, even though it’s declined a tad, you’re still looking at a billion, around a billion devices a year. So, now that’s incredible. And it’s incredible that no matter how much technology comes down the line, nobody, I’ve never heard anybody who’s really excited and happy about their battery life. So we keep increasing capability with CPU, GPU, NPU, ISPs, and we’re creating all these energy sucking devices and everybody’s trying to figure out, hey, how do I not hit memory all the time? Because it just drains the battery, but as you know, more memory is a better experience. So as opposed to going out to storage. So anyways, just wanted to get that clarification in.

Daniel Newman: Pat. It’s funny because I’m still back in the LPDDR5X, say it five times fast. When you guys were going back and I really wanted to [inaudible 00:14:44]have a little bit of a lighter moment because this stuff gets really technical and, Thy, you do a nice job of explaining it. I want to double-click on something you talked a little bit about, you were talking about the challenges of DRAM scaling when you were talking about the innovation and just for everybody out there to get to 1-beta was a lot of work. So again, these technical terms, sometimes it gets lost, more memory, lower power consumption, and now with every chip company constantly kind of dumping their newest thing on the market, I think some of the great work gets lost in translation. So can you just give a little bit more kind of history, the challenges of DRAM scaling? Because you guys, this is something you’re really uniquely doing that’s gotten you into this unique position in the market.

Thy Tran: Yes. So if you look back some years ago, when you asked how to do DRAM scaling, it was capacitor, capacitor, capacitor. So in a DRAM cell we have very, it’s very simple. It’s two basic elements, a capacitor and a transistor, right? And then we have billions of those. And in terms of capacitor, that was our holy grail. But now we have to focus on the access transistor. And not only that, but the connection. So how we connect the transistor to the capacitor, how we connect the transistor to what we call the word line. Then also the bit line just to connect to the rest of the circuit. And then as I noted earlier, besides that memory cell array, which we spent most of our focus on, now we have to deploy advanced CMOs technology. Now our logic industry has been at the forefront and the reason behind that is they’re not limited by what we call the thermal budget of the DRAM flow, which is basically temperature and time and DRAM for the memory cell array integration requires very high thermal budget, so long time and high temperature.

So not only do we have to take care of that basic fundamental transistor, capacitor, we have to deal with the rest. And we push the envelope of CMOs technology innovations by leveraging the learning from logic, but also we have to innovate to integrate that with the rest of the flow so that the memory array has the best performance and then the rest of the circuit, the sense amplifier, as I noted earlier, the local word line driver and the periphery circuits have to optimize timing that allows you to basically reduce the power consumption. So basically just dissipate less heat and give you longer battery lifetime. And also be as fast as we can. We all want our data at the snap of our finger. And as you noted earlier that no one’s happy with their battery life. You can never have enough battery life. So you can never have enough memory, but you can never have enough battery life either. So yeah, basically we leave no stone unturned.

Patrick Moorhead: Yeah. Again, another great explanation of something that is so difficult to get your head around. I mean, in the old days we used to consider, hey, we’re going to do a shrink and it’s easy, right? But the fact is that every five years we talk about how the industry has run out of gas, we can’t shrink it anymore. But through the innovation of people like your team and Micron, you’re able to do that. I’m still a little bit stuck Daniel on the LPDDR5X five times, but I did want to drill in, and this is a future statement. You talked a little bit about some other applications and what we could expect, but you’re very much in any kind of device on the planet, whether it’s a car, a server, a desktop, pc, pretty much anything that requires some high-speed memory. So what benefits does this new process node 1-beta bring to the rest of your segments? I know you’re not launching those yet, but I think the audience would like to hear what it brings to the table, performance, power, things like that.

Thy Tran: It’s absolutely all of the above, but I want to go back on the LPDDR5X, easiest to say LP5X. So that’s the short version of it.

Patrick Moorhead: Come on. It’s fun, keep going.

Thy Tran: Yeah. But with respect to the benefits, so the way that we develop the portfolio, it’s not only to be robust for one product family, it has to be able to meet the requirements for the broader market segments. And so the ability to design it so that the process design point is most optimized, it’s may not be the sweetest spot for every single device, but it’s somewhere where it’s optimal enough for where the entire process window can facilitate all the requirements for the different products. We have numerous other product plan and quite a few are in the works already. So the requirements, for example, for graphics in terms of even faster speed and especially high bandwidth memories.

Patrick Moorhead: How did I forget about graphics? I did though.

Thy Tran: Yeah. And as you know, we’ve led in graphics as well. So graphics, high bandwidth memories have very different requirements compared to low power, right? Because you can design the process design point to optimize more for speed instead of, and it’s more forgiving for power and also especially for cost margins, right? So the way that we designed it, you can add a little bit more bells and whistles from the process side to enhance that. So it’s basically a toolkit where you have all of the tools of the knobs to tweak and turn so that you enhance for each individual product. So it’s a base platform that is so robust that we’re able to deliver that, so that’s really exciting.

Patrick Moorhead: And I am seeing some power budgets on the latest graphics cards that are absolutely stunning. And by the way, we can say GDDR6 six times fast as well. No, sorry to cut you off, but you’re right. The more power efficient you can be, for example, on a graphics card, the more power budget that you have to put in the processor, so.

Daniel Newman: I think her examples of the knobs or the levers, right? It’s always a bit of a give and take. If you’re using a lot of power for one thing and how that impacts, I could use a little of that rendering and graphics to get this bright sun. It was so beautiful [inaudible 00:22:32] and then the exposure just comes through and it’s like, well I guess if anybody’s face in this group is going to get washed out, it should be mine.

But in all serious, Thy, you took a really complicated topic and I think you’ve made it digestible. And that’s really what we like to focus on here on the Six Five, we love the semiconductor space. We love and know that the technology that is being built by companies like yours at Micron is changing the world, changing the dynamics of compute and what companies are able to do in the data center on mobile and on of course on our PCs. And I just want to thank you so much for joining us today, Thy, on the show, you’re now an alumni of the Six Five and we’re going to have to have you back on really soon.

Thy Tran: Yay. Thank you. Thank you, Patrick. Thank you Daniel. So I just want to say, close with this note, Micron again can maintain our leadership position in both DRAM and NAND. And for the past few years, working on the world’s most advanced DRAM node was really a labor of love for our 1-beta team. And it’s been an extraordinary engineering feat one that we’re super proud of. And so we look forward to sharing more memorable moments with you.

Daniel Newman: Well, congratulations again, great news. We’ll be sure to have this out and everybody out there check out the show notes, we’ll have links to more information from Micron and of course this great conversation with Thy. For this episode though, it’s time to say goodbye. Hit that subscribe button, join us here for all of our weekly Six Five shows and our insider edits. We have a lot of great executives just like Thy, that join the show week in and week out. And we appreciate everyone out there in our community. But like I said, time to say goodbye. Have a beautiful day everyone. See you later.


Author Information

Daniel is the CEO of The Futurum Group. Living his life at the intersection of people and technology, Daniel works with the world’s largest technology brands exploring Digital Transformation and how it is influencing the enterprise.

From the leading edge of AI to global technology policy, Daniel makes the connections between business, people and tech that are required for companies to benefit most from their technology investments. Daniel is a top 5 globally ranked industry analyst and his ideas are regularly cited or shared in television appearances by CNBC, Bloomberg, Wall Street Journal and hundreds of other sites around the world.

A 7x Best-Selling Author including his most recent book “Human/Machine.” Daniel is also a Forbes and MarketWatch (Dow Jones) contributor.

An MBA and Former Graduate Adjunct Faculty, Daniel is an Austin Texas transplant after 40 years in Chicago. His speaking takes him around the world each year as he shares his vision of the role technology will play in our future.


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