Analyst(s): Brendan Burke
Publication Date: July 29, 2026
At the 2026 DAC Chips to Systems Conference, Synopsys unveiled a fully autonomous design verification agent, claiming up to 50x faster time-to-validated RTL; its first fully autonomous CAE workflow; and the first autonomous EDA workflows on Microsoft Discovery with AMD. Cadence introduced its AuraStack AI Super Agent to complete a silicon-to-system agent portfolio, and Siemens added self-verifying agents to its Fuse EDA AI Agent system, all built on NVIDIA’s agentic AI stack. Agentic chip design moved from task assistance to long-running autonomy across all three EDA leaders.
What is Covered in This Article:
- Synopsys unveiled a fully autonomous, long-running design verification agent claiming up to 50x faster time-to-validated RTL with 20% additional coverage improvement, its first fully autonomous CAE workflow for thermal management built with Ansys Icepak, and an expanded portfolio of more than 20 GPU-accelerated products, including an 18x PrimeSim SPICE speedup.
- One day later, Synopsys announced the industry’s first autonomous EDA workflows on Microsoft Discovery, developed with Microsoft and actively evaluated by AMD, with early results showing 25-40% reductions in debug cycle time.
- Cadence introduced the AuraStack AI Super Agent for PCB and advanced packaging, citing up to 20x faster multiphysics performance, and positioned its four AI Super Agents as the industry’s first complete silicon-to-system agentic stack.
- Siemens expanded its NVIDIA partnership around self-verifying agentic workflows in its Fuse EDA AI Agent system, claiming more than 10x faster library characterization in the Solido Characterization Suite with a 5x to 10x reduction in token costs.
- NVIDIA supplied the common platform, expanding its Agent Toolkit with PhysicsNeMo and CUDA-X libraries and reporting Nemotron 3 Ultra leads open models in agentic RTL coding, while deploying its Vera CPU across internal EDA workflows with vendor-reported 1.5x gains on Synopsys VCS and Cadence Jasper.
The News: At the 2026 DAC Chips to Systems Conference in Long Beach, Synopsys announced fully autonomous, long-running agentic workflows for chip and electronics system design, enabled by NVIDIA Nemotron on NVIDIA’s accelerated computing platform and secured by the NVIDIA OpenShell runtime, headlined by a design verification agent that orchestrates the entire chip verification cycle and the company’s first fully autonomous CAE workflow for electronics thermal analysis. On July 27, Synopsys separately introduced the first autonomous EDA workflows available for evaluation on Microsoft Discovery, developed with Microsoft and actively evaluated by AMD. Cadence introduced the AuraStack AI Super Agent for PCB and advanced packaging design, completing an agent portfolio spanning the electronic system design flow, and Siemens announced self-verifying agentic AI workflows for its Fuse EDA AI Agent system. NVIDIA anchored the announcements by expanding its Agent Toolkit with PhysicsNeMo and CUDA-X libraries and disclosing that it is deploying its Vera CPU across its own EDA workflows.
Synopsys, Cadence, and Siemens Take Agentic Chip Design Autonomous at DAC
Analyst Take: DAC 2026 marks the moment agentic chip design crossed from task assistance to long-running autonomy across all three EDA leaders at once. Synopsys made the largest single move, pairing a fully autonomous design verification agent that claims up to 50x faster time-to-validated RTL with its first fully autonomous CAE workflow and, one day later, the first autonomous EDA workflows on Microsoft Discovery with AMD. Cadence completed its silicon-to-system agent portfolio with AuraStack, and Siemens staked out self-verification as its differentiator. At Computex in June, the agentic EDA race was a two-vendor contest over autonomy depth versus multiphysics breadth. Six weeks later, all three EDA leaders are shipping toward the same destination on NVIDIA’s stack, and the chipmakers themselves, NVIDIA and AMD, have become the lead customers pulling the roadmaps forward.
Synopsys Pairs Autonomy Depth With Multi-Vendor Breadth
Synopsys answered the depth-versus-breadth question by claiming both. For EDA depth, the fully autonomous design verification workflow deconstructs verification goals from specification and design inputs and drives specialized agents in a closed loop from test plan generation to coverage closure and debug. The company-disclosed result, up to 50x faster time-to-validated RTL with an additional 20% coverage improvement, targets the single largest bottleneck in chip development and directly answers the more-than-40x RTL validation figure Cadence claimed for ChipStack at Computex.
The breadth play extends in three directions at once: the first fully autonomous CAE workflow, which uses Ansys Icepak to autonomously execute thermal simulation setup, pre-processing, and post-processing for GPU cooling; autonomous analog and mixed-signal workflows claiming up to 3x productivity gains on Custom Compiler Layout Synthesis; and more than 20 GPU-accelerated EDA and multiphysics products, including an 18x PrimeSim SPICE speedup and up to 50x QuantumATK gains enabled by cuEST.
The Microsoft Discovery announcement with AMD completes the picture. By landing the first EDA workflows on Discovery, with a debug closure agent showing early 25-40% cycle time reductions and Fusion Compiler running on Azure, Synopsys became the only EDA vendor operating credible agentic workflows on two compute platforms. The same week Synopsys deepened its NVIDIA dependence, it ensured agentic chip design will not consolidate around a single vendor’s processors by default.
Cadence Completes the First Silicon-to-System Agent Portfolio
Cadence’s counter is architectural completeness. With AuraStack joining ChipStack for verification, InnoStack for digital implementation, and ViraStack for custom and analog design, Cadence now claims the industry’s first complete silicon-to-system agentic stack, spanning architecture through manufacturing signoff. AuraStack itself targets the domain Futurum identified as Cadence’s structural gap at Computex: multiphysics. Built on NVIDIA Agent Toolkit and Nemotron 3 Ultra and accelerated by CUDA-X libraries including cuDSS on the Millennium M2000 platform, AuraStack coordinates agents across planning, implementation, and multiphysics analysis, with Cadence citing up to 20x faster multiphysics performance across signal integrity, power integrity, electromagnetic, and thermal simulation, up to 15x faster design workflows, and up to 2x faster time to market, all company-supplied figures.
The strongest validation signal is NVIDIA engineers already applying AuraStack to the company’s own AI infrastructure challenges, extending the reference relationship that began with Jensen Huang’s endorsement of ChipStack. Cadence is also hedging into the compute layer, optimizing Jasper for the NVIDIA Vera CPU. Where Cadence still lags is an Ansys-equivalent physics portfolio pending the integration of Hexagon design & engineering software, which is why its multiphysics claims lean on NVIDIA’s libraries and hardware. Synopsys leans on integrated Ansys engines, a distinction that will matter as physical closure becomes the competitive battleground.
Siemens Stakes Its Claim on Self-Verifying, Physics-Validated Agents
Siemens took the most distinctive intellectual position at DAC: autonomy is not the goal, trusted autonomy is. Its expanded NVIDIA partnership centers on self-verifying agentic workflows, long-running agents in the Fuse EDA AI Agent system that continuously validate their decisions against deterministic, physics-based EDA engines rather than trusting model outputs. The Solido Characterization Suite delivers a company-reported 10x reduction in library characterization turnaround with a 5x to 10x reduction in token costs, and STMicroelectronics’ non-volatile memory team publicly endorsed the new Solido Layout Analyzer for cutting weeks of debug time. Integration with Siemens’ Intelligence Center X also extends agent orchestration beyond EDA into design, manufacturing, and supply chain operations, a reach neither Synopsys nor Cadence can match.
The self-verification framing is more than marketing. As Futurum argued at Computex, hardware engineers treat autonomy-level labels as marketing until proven, and grounding agent decisions in signoff-grade physics engines is the most credible answer yet to that skepticism. Siemens’ agentic claims remain narrower than its rivals’ full-flow autonomy demonstrations, pending forthcoming releases.
NVIDIA and AMD Are the Compute Anchors Pulling the Roadmaps
Beneath the three EDA announcements sits a common platform and a revealing customer pattern. NVIDIA supplies the reasoning layer with Nemotron 3 Ultra, which it reports leads open models in agentic RTL coding on the Comprehensive Verilog Design Problems benchmark via the ACE-RTL agent, a vendor-run result awaiting independent replication. It supplies the governance layer with OpenShell, adopted by all three vendors, and the solver layer with CUDA-X, including the new cuISS iterative sparse solver library and cuEST, for which Samsung, Synopsys, and TSMC report up to 50x quantum-chemistry speedups. With Vera, NVIDIA now extends into the CPU-bound verification farms that dominate EDA compute budgets, reporting up to 1.5x higher performance on Synopsys VCS and Cadence Jasper from early internal testing at matched core counts. EDA farms are exactly the latency-sensitive, throughput-heavy workload that decides which architectures win agentic CPU growth.
The demand side is equally telling. NVIDIA is designing its next chips with these agents and CPUs, and AMD is actively evaluating Synopsys’ Discovery workflows for its next-generation products, with AMD Corporate Fellow Alex Starr calling AI-driven root cause analysis a paradigm that accelerates both design velocity and silicon quality. Agentic chip design is being pulled by the two companies with the most acute design-throughput constraints, not pushed by EDA marketing, and that demand-pull inverts the industry’s traditionally conservative adoption pattern.
What to Watch:
- Whether Synopsys’ H2 2026 general availability arrives with named customers and audited baselines behind the 50x verification claim, and whether AMD converts its Microsoft Discovery evaluation into a production commitment for next-generation silicon.
- Whether Cadence or Siemens follows Synopsys onto Microsoft Discovery or an equivalent non-NVIDIA platform, which would confirm that multi-vendor hedging is structural rather than a Synopsys-specific strategy.
- How Cadence answers Synopsys’ owned Ansys physics engines as physical closure becomes the battleground, and how quickly Siemens broadens self-verifying agents beyond characterization into full-flow autonomy.
- Whether frontier AI labs attempt to ground general coding agents directly in EDA flows, testing the tool-integration moat all three incumbents are counting on.
Synopsys summarized all its DAC advancements in a news release on its website.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.
Other Insights From Futurum:
Cadence AuraStack Extends Agentic Leadership Toward Advanced Packaging Design
Will the First Wave of Synopsys Multiphysics Fusion Start the Next Wave of AI Chip Designs?
Cadence and Synopsys Accelerate Agentic EDA Race at Computex
Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
