The News: Marvell is extending its collaboration with Taiwan Semiconductor Manufacturing Company (TSMC) to develop a breakthrough technology platform to produce 2nm semiconductors optimized for accelerated infrastructure. Read the full press release on the Marvell website.
Marvell TSMC: Stimulating 2nm Accelerated Infrastructure Innovation
Analyst Take: Marvell is extending its collaboration with TSMC to produce 2nm semiconductors targeted at accelerated infrastructure optimization. Reinforcing the Marvell 2nm platform is its intellectual property (IP) portfolio that covers the vast array of infrastructure requirements, consisting of high-speed long-reach SerDes at speeds above 200 Gbps, processor subsystems, encryption engines, system-on-chip fabrics, chip-to-chip interconnects, and a variety of high-bandwidth physical layer interfaces for compute, memory, networking, and storage architectures.
We see that such technologies can serve as the silicon foundation for driving cloud-optimized custom compute accelerators, Ethernet switches, optical and copper interconnect digital signal processors, and other devices for powering AI clusters, cloud data centers, and other accelerated infrastructure. Increasingly, investing in platform components such as advanced packaging and interconnects is essential for accelerated infrastructure because breakthroughs at the platform level can ease data bottlenecks that can encumber performance of the entire system as well as decrease the cost and time-to-market for multichip solutions designed for running the most intricate applications.
In the post-Moore’s Law epoch, new approaches are essential to optimizing costs—on a normalized costs per transistor basis—using scaling and integration, materials innovation, and advanced packaging to ensure competitiveness now exemplified by the broadening of Marvell’s alliance with TSMC to produce 2nm semiconductors targeted at accelerated infrastructure optimization.
The new collaboration focused on 2nm infrastructure silicon follows Marvell innovative breakthroughs in 5nm and 3nm working with TSMC. For instance, Marvell has developed and demonstrated high-speed, ultra-high-bandwidth silicon interconnects produced on TSMC 3nm process. Marvell’s silicon building blocks in this node include 112G XSR SerDes (serializer/de-serializer), Long Reach SerDes, PCIe Gen 6/CXL 3.0 SerDes, and a 240 TBps parallel die-to-die interconnect.
The building blocks are part of Marvell’s continued execution of its strategy to develop a comprehensive silicon IP portfolio for designing chips that can increase the bandwidth, performance, and energy efficiency of rapidly evolving data infrastructure. These technologies also support all semiconductor packaging options from standard and low-cost Redistribution Layers (RDL) to silicon-based high-density interconnect.
Plus, I find that Marvell achieved a semiconductor industry breakthrough by sampling and commercially releasing 112G SerDes, following on advancing the market presence of its data infrastructure portfolio based on TSMC’s 5nm process. To review, SerDes and parallel interconnects serve as high-speed pathways for exchanging data between chips or silicon components inside chiplets. Together with 2.5D and 3D packaging, these technologies are built to eliminate system-level bottlenecks to advance the most intricate semiconductor designs. SerDes also helps reduce pins, traces, and circuit board space to reduce expenses. A rack in a hyperscale data center, for instance, could contain tens of thousands of SerDes links.
For fast expanding AI/GenAI workloads, 2nm will prove essential for providing the massive gains required across transistor density, area, power, and performance factors. As a result, I find that Marvell can offer sharply differentiated analog, mixed-signal, and foundational IP to deliver accelerated IP innovation. Fundamentally, Marvell’s modular approach to semiconductor research and design that focuses first on qualifying foundational analog, mixed-signal IP and advanced packaging is well-suited for a vast array of devices.
Marvell and TSMC: A Winning 2nm Combination
Marvell’s TSMC 2nm announcement aligns adeptly with TSMC’s own progress with preparing volume production of 2nm chips, which TSMC anticipates will begin in 2025, ushering built-in energy efficiency and density breakthroughs. TSMC is already addressing geopolitical issues that its semiconductor customers must factor into their 2nm manufacturing decision-making.
To review, TSMC already operates a fab in Camas, Washington, and has design centers in San Jose, California, and Austin, Texas. TSMC has invested $12 billion in building an advanced semiconductor manufacturing fab (N4/4nm process in Phoenix, Arizona, with volume production anticipated to begin in H1 2025). Moreover, TSMC has committed to building a second fab in Phoenix, further boosting its total investment to $40 billion. In March 2024, TSMC shared that it is in line for over $5 billion in federal grants to help facilitate completion of its facilities in Phoenix. The bottom line is that it will become increasingly difficult for Samsung and Intel to challenge TSMC’s overall market leadership primarily on geopolitical grounds.
From my view, TSMC is well-positioned to advance 2nm capabilities in relation to its advanced foundry rivals Samsung and Intel. For instance, Samsung attained first-to-market status in the mass production of 3nm chips, however, has encountered difficulties with its yield rate, which is the amount of chips produced that are considered shippable to customers. Reports indicate that Samsung’s yield rate for its simplest 3nm chip is only 60%, which I find problematic for producing increasingly complex chips akin to NVIDIA GPUs as well as Apple’s A17 Pro. This also does not bode well for Samsung to assert first-to-market claims for producing 2nm chips as it has not fully resolved ongoing yield issues with 3nm production.
Also, Intel is advocating its 18A (1.8nm class) node in preparation for its production in H2 2024, offering free test production to chip design outfits. Intel is in the process of demonstrating that its 18A node can match or exceed the density, performance, and energy efficiencies to TSMC’s existing 3nm as well as unfolding 2nm capabilities. The upshot is that both Samsung and Intel have a good deal to prove beforehand in mounting a direct competitive challenge to TSMC’s 2nm proposition that go beyond geopolitical considerations.
Key Takeaways: Marvell and TSMC Ready to Accelerate 2nm Innovation
I believe that Marvell’s extension of its alliance with TSMC provides the semiconductor design and development path vital to spurring ecosystem-wide accelerated infrastructure innovation underpinned by 2nm process technology. Marvell and TSMC’s combined acumen in key technology areas such as process and packaging can ensure improved go-to-market and business outcomes, especially for OEM/ODM device customers.
Disclosure: The Futurum Group is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of The Futurum Group as a whole.
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Author Information
Ron is an experienced, customer-focused research expert and analyst, with over 20 years of experience in the digital and IT transformation markets, working with businesses to drive consistent revenue and sales growth.
Ron holds a Master of Arts in Public Policy from University of Nevada — Las Vegas and a Bachelor of Arts in political science/government from William and Mary.
