The News: Marvell demonstrated high-speed, ultra-high bandwidth silicon interconnects produced on Taiwan Semiconductor Manufacturing Company’s (TSMC) 3 nanometer (3nm) process. Marvell’s building blocks in this node include 112G XSR SerDes (serial/de-serializer), Long Reach SerDes, PCIe Gen 6 / CXL 3.0 SerDes, and a 240 Tbps parallel die-to-die interconnect. Read the Marvell Press Release here.
Marvell Breaks on Through to the 3nm Process Realm
Analyst Take: Marvell’s 3nm debut pushes the innovation envelope across the semiconductor market, representing good news for data infrastructure environments such as data centers. The new building blocks are integral to Marvell’s portfolio strategy of developing a comprehensive silicon IP portfolio for designing chips that advance the bandwidth performance and energy efficiency of data infrastructure. These technologies support the full range of semiconductor packaging options from standard and low-cost Redistribution Layers (RDL) to silicon-based high-density interconnect.
The 3nm offering follows Marvell’s initial data infrastructure SerDes silicon based on TSMC’s 5nm process. The new offering is combined with 2.5D and 3D packaging for advanced semiconductors and aims to decrease the required number of pins and traces, as well as circuit board space, that can yield decreased costs across the data infrastructure value chain. With data center capacity and bandwidth demands expected to skyrocket into the foreseeable future due to major drivers such as AI and cloud compute requirements, I anticipate that Marvell SerDes link technology can prove a significant cost difference maker as well as cost saver.
Marvell incorporates its SerDes and interconnect technologies across its mainstay silicon offerings including Alaska Ethernet physical layer (PHY) devices, Bravera storage controllers, Brightlane automotive Ethernet chipsets, custom ASICs, OCTEON processors, PAM4 & coherent DSPs, and Teralynx switches. For instance, Marvell die-to-die interconnects can deliver data transfer speeds at up to 240 Tbps, which the company touts can be 45% faster than available alternatives in multichip packages.
I see the 3nm process collaboration between Marvell and TSMC as essential to driving integrated circuit (IC) development in maintaining and accelerating hardware performance and signal integrity while conserving and improving energy efficiencies. For context, the 3nm process enables 250 million transistors per square nanometer assuring the higher transistor counts key to lowering power consumption while improving performance with the equivalent power usage requirements. Also, stay tuned for the emerging 2nm process to deliver 310 million transistors in the same area, which I expect TSMC to have market ready by 2025.
With the Marvell deal, TSMC gains a high-profile customer endorsement and engagement as it battles Samsung for winning more foundry mindshare and customers in the nascent 3nm silicon manufacturing space. Of note, TSMC is already allied with Apple to use 3nm-based chips in Apple’s upcoming MacBook series and iPhone 15 Pro models.
In addition, Broadcom, Qualcomm, MediaTek, NVIDIA, and AMD have all placed their 3nm chips orders with TSMC and are in queue to take advantage of the foundry’s N3 and N3E process manufacturing. From my view, Marvell gains a near-term sales and marketing competitive edge over main data infrastructure silicon rival Broadcom by arriving in the market beforehand with the completed sampling and commercial release of its 3nm chipset portfolio.
Key Takeaways: Marvell Allies with TSMC for 3nm Portfolio Debut
Overall, I believe that Marvell’s new 3nm portfolio can broaden and catalyze data infrastructure market adoption of Marvell interconnect, SerDes, and parallel interface features as computing system applications, such as cloud, AI, networking, 5G, automotive, and custom solutions, expand in scope, intricacy, and use case range. Now I anticipate that Marvell’s parallel interface and SerDes technology can prove integral in delivering the platform key to advancing bandwidth, latency, and power efficiency capabilities throughout the data infrastructure ecosystem.
Disclosure: The Futurum Group is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of The Futurum Group as a whole.
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Image Credit: Marvell
Author Information
Ron is an experienced, customer-focused research expert and analyst, with over 20 years of experience in the digital and IT transformation markets, working with businesses to drive consistent revenue and sales growth.
Ron holds a Master of Arts in Public Policy from University of Nevada — Las Vegas and a Bachelor of Arts in political science/government from William and Mary.
