IBM has unveiled the world’s first sub-1nm chip technology at the 7 angstrom node, built on a new three-dimensional “nanostack” transistor architecture that vertically stacks and staggers transistors. Nanostack is projected to deliver up to 50% more performance or 70% greater energy efficiency than IBM’s 2nm node, and 40% SRAM scaling, the first meaningful SRAM density gain in over a decade. The IBM nanostack architecture, not the node name, is the breakthrough that resets the roadmap for AI-era compute.
What Is Covered in This Article:
- IBM introduced the world’s first sub-1nm chip technology at the 0.7nm/7-angstrom node, powered by its new three-dimensional nanostack transistor architecture.
- Nanostack moves scaling into the Z dimension for the first time.
- Defining a roadmap from 7A to 1A across the next decade
- Collaboration on High-NA EUV lithography with R&D and fabrication partners
- Execution risks and adoption timeline for nanostack architecture
The News: IBM has introduced the world’s first sub-1 nanometer chip technology at the 0.7nm, or 7 angstrom, node, built on a revolutionary new transistor architecture called nanostack. The chip packs nearly 100 billion transistors onto a die about the size of a fingernail and is projected to deliver up to 50% more performance or 70% greater energy efficiency than that 2nm node. IBM also reported 40% SRAM scaling enabled by nanostack, a step change the industry has not seen in over a decade. The work, conducted with partners at IBM’s Albany, New York research facility, points to a path to production within about five years.
Look Past IBM’s 0.7nm Label: Nanostack Architecture Is the Real Breakthrough
Analyst Take: IBM’s sub-1nm announcement has been reported almost everywhere as a node-name story. Modern node names are decoupled from any physical dimension; IBM’s leadership said as much in our briefing, noting that “0.7nm” is an industry benchmarking label, not a measured gate length or pitch. The IBM nanostack architecture is the actual breakthrough here, and it deserves to be evaluated on its structural merits rather than on a number chosen for the press release. Nanostack is the first 3D, nanosheet-based transistor design to stack and stagger transistors in the vertical (Z) dimension, unlocking both the efficiency gains and, more importantly, the return of SRAM scaling.
The Node Name Is Marketing. The Architecture Is the Breakthrough.
For more than 60 years, since the MOSFET arrived in 1959, transistor scaling has happened in two dimensions — the X and Y axes of the wafer. IBM’s nanostack architecture introduces a genuine third axis. Each nanostack cell comprises two nanosheet transistors built on separate wafers and joined by ultra-thin dielectric bonding, with three sheets per device, each sheet roughly 5nm thick and separated by a 9nm suspension. Because the two transistors are bonded rather than patterned together lithographically, the top and bottom devices can be optimized independently — different channel materials, dielectrics, and metals on each layer. That single property is why IBM is careful to call nanostack a platform rather than a one-off device: it projects a roadmap from 7A through 5A, 3A, 2A and onward to 1A, roughly a decade of scaling, with multi-layer stacking signposted beyond that.
SRAM Scaling Ends a 12-Year Stall
This is where the announcement should gain the closest attention. Logic cell height has kept shrinking but SRAM bitcell height and area scaling have been effectively flat for over a decade. The reason is the N-to-P spacing required for reliable patterning in a 2D layout. Every CMOS gate pairs an N-type transistor with a P-type transistor. In every chip shipping today, the two sit side by side on the same plane, separated by a minimum “N-P spacing.” That gap is not set by how small the transistor can be made; it is set by the need to pattern two different work-function gate metals next to each other, to isolate the n+ and p+ source/drain regions, and to prevent latch-up. Critically, the N-P spacing barely shrinks from node to node. In logic, back-end metal-pitch scaling hid the problem; in SRAM, whose six-transistor bitcell is laid out as an N-P-N-P sequence, the spacing dominates the cell, which is why SRAM area has been essentially flat for over a decade
Nanostack stacks the N device directly beneath the P device, so the lateral gap rotates into a thin vertical bonding dielectric and effectively disappears. When Nanostack’s N and P devices are stacked vertically with only a thin bonding dielectric between them, there is no N-P spacing to scale and the constraint is removed. In the VLSI 2026 paper “Area and Performance of Staggered-Channel Nanostack SRAM Bitcells,” IBM’s Chen Zhang and colleagues demonstrate the enabling structure — the top-bottom gate-merge contact — fabricated on silicon for the first time, with good overlay alignment. Their analysis shows more than 40% SRAM cell-height reduction versus state-of-the-art non-stacked cells, achieved entirely within today’s patterning capability.
Unlocking the Next Generation of Dense-SRAM accelerators
The SRAM stall has a price tag. At TSMC’s N3, the six-transistor SRAM bitcell came in around 0.0199 square microns, barely 5% smaller than N5’s 0.021, and the N3E variant did not scale at all. As logic kept shrinking around it, SRAM’s share of advanced-chip die area has climbed toward 30% and beyond. Because SRAM stopped scaling while compute did not, every additional megabyte of on-die memory costs more area and more money at exactly the moment AI silicon needs the most of it.
That is the constraint dense-SRAM accelerators run into first. Weights, activations, and the key-value caches inference are kept in SRAM to stay close to compute and avoid the memory wall. Architectures from Cerebras, Groq, and SambaNova commit hundreds of megabytes of SRAM on-die, and even mainstream GPUs devote tens of megabytes to L2 cache. A 40% reduction in SRAM cell height is roughly 40% more SRAM in the same area, or the same capacity at lower cost — several nodes’ worth of SRAM scaling in a single architectural step, which lets designers grow KV cache capacity without growing the die.
Capacity is only half of it. IBM’s VLSI 2026 results show about 20% lower percell wordline capacitance and a substantial wordline RC reduction, with backside bitlines lowering bitline resistance — faster, lower-energy SRAM access, which is often the real accelerator bottleneck. Because nanostack optimizes its top and bottom transistors independently, the SRAM devices can also be tuned for read/write margin separately from logic, supporting the low-voltage operation these chips rely on for efficiency. Nanostack restarts SRAM scaling exactly when accelerators are most SRAM-bound.
Collapsing 3D Integration Into the Transistor
Nanostack is the next rung on a ladder the whole industry has been climbing, not a standalone leap. 3D packaging already stacks whole dies using hybrid bonding, but at the package level. Backside power delivery put routing on both sides of the wafer for the first time: Intel’s PowerVia is shipping on its 18A node, and TSMC’s Super Power Rail is slated for N2-class production around 2026. Gate-all-around nanosheet — IBM’s own invention — was commercialized by TSMC’s N2 and Intel’s 18A RibbonFET, replacing FinFET at the leading edge. The agreed next step across imec, TSMC, and Intel is CFET, which stacks N over P monolithically under a shared gate, but the industry does not expect CFET in production until roughly 2031.
Nanostack takes the hybrid-bonding and backside-power techniques those companies proved at the package and wafer level and pushes them down into the transistor pair itself: it sequentially bonds two separately optimized nanosheet wafers and staggers them, rather than building a monolithic CFET. IBM’s argument is that this sequential, staggered approach avoids CFET’s shared-patterning constraints, allows the top and bottom transistors to use different materials, and reaches production faster on IBM’s stated timeline, in about five years.
Why IBM Can Capture More of This Breakthrough Than It Did with Nanosheet
IBM invented gate-all-around nanosheet but did not capture most of its value. After selling its chip business to GlobalFoundries in 2015, IBM stopped manufacturing at volume, and the economics of GAA flowed to the foundries that built fabs around it — Samsung first to production in 2022, TSMC at N2, and Intel with RibbonFET. IBM monetized nanosheet mainly through IP licensing, its Albany research alliance, and as a fabless designer whose own Telum and Power chips are built on partners’ leading-edge nodes. Others got to sell the wafers.
Nanostack arrives into a different structure. For the first time since exiting its fabs, IBM has a dedicated, aligned manufacturing partner in Rapidus — a venture purpose-built around IBM-derived technology. Rapidus’s IIM-1 line in Hokkaido is already running a 2nm GAA process developed with IBM, with IBM engineers on-site and an active technology transfer, mass production targeted around 2027. Unlike Samsung or TSMC, which set their own competing roadmaps, Rapidus’s roadmap is IBM’s roadmap, and Nanostack is the natural next technology to flow down that pipe. Just as important, IBM is engaged at the tooling layer at the right moment: it is co-developing High-NA EUV processes and resists at Albany with Lam Research, Tokyo Electron, and SCREEN, while Rapidus deploys ASML’s High-NA EUV tool.
Because nanostack’s hard problems are process problems — wafer bonding, an ultra-thin defect-free dielectric, 3D metrology — sitting inside both the device architecture and the process enablement, with a captive-style manufacturing partner, is exactly the leverage IBM lacked during the GAA era. The caveat is equally important: Rapidus has not yet shipped volume 2nm, so IBM’s stronger position is contingent on its partner proving yield at scale. If Rapidus stumbles, IBM is back to licensing nanostack to foundries that will prioritize their own processes.
In the analyst briefing I asked IBM whether the architecture benefits from High-NA EUV. IBM’s answer was unambiguous — the back-end interconnect must keep scaling below 18nm, and the company considers High-NA EUV mission-critical for a single-exposure solution at that pitch, with an ASML High-NA tool being installed at Albany and a metal-oxide resist under evaluation. IBM’s Albany alliance is built to co-develop the High-NA recipe alongside ASML, Lam Research, Tokyo Electron, and SCREEN, and Rapidus is one of the few production lines actually running a High-NA tool today. Together they can climb the High-NA learning curve while most of the industry waits, converting early process maturity into a yield-and-readiness advantage at the angstrom-class back end that nanostack depends on
Outlook for EDA and Materials Innovaiton
Every marquee figure is projected or simulated, benchmarked against IBM’s 2nm node, not measured on a shipping product. IBM has validated the hard physics, which is genuinely more than a slideware demo. But the company is explicit that production is roughly five years out, and IBM does not manufacture at volume itself. The EDA tools needed to design 3D at the transistor level do not yet exist, and IBM is candid that they “need to arrive.” In a separate question I raised the harder commercialization issue — thermal, signal integrity, and power-delivery challenges for yield, and whether materials innovation would be required. IBM agreed on both counts: moving from 2D to 3D shifts the dominant problem from electrical to mechanical and thermal, and IBM says it is now embedding thermal and mechanical co-design into the technology definition from the outset rather than treating it as an afterthought. It is also actively searching for a more thermally conductive, ultra-thin, defect-free bonding dielectric — a material innovation the structure will live or die on.
What to Watch:
- IBM and partners must develop new High-NA EUV processes for sub-18nm interconnect single-exposure
- IBM is working with EDA partners to embed thermal and mechanical co-design from the start
- A more conductive, ultra-thin, defect-free bonding dielectric is the key material innovation to watch
- Rapidus has not yet proven volume yield, and nanostack’s commercialization rides on it doing so
- IBM targets production in roughly five years, so watch for hardware proof points at upcoming conferences (VLSI, IEDM, DAC).
See the full announcement on the IBM Newsroom.
Sources
- IBM Debuts World’s First Sub-1 Nanometer Chip Technology
- IBM Q1 FY 2026 Earnings Show Software Growth and Mainframe AI Monetization
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Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
