Analyst(s): Brendan Burke
Publication Date: June 4, 2026
Intel CEO Lip-Bu Tan’s COMPUTEX 2026 keynote covers Xeon 6+ on the Intel 18A process, Rackscale Blueprints with SambaNova and Foxconn, Vector Core Compute disaggregated inference, the Google IPU and Ericsson purpose-built silicon, Perplexity hybrid agentic inference on Core Ultra Series 3, and the CPU-to-GPU ratio shift toward parity.
What is Covered in This Article:
- Reorganizing the Intel agentic AI strategy around PC, edge, and physical AI, foundational data centers, and emerging intelligence centers
- Xeon 6+ launches as Intel’s first 18A data center CPU
- Rackscale Blueprints, the SambaNova and Foxconn collaboration, and Vector Core Compute’s disaggregated inference cloud move Intel from selling sockets to integrating systems.
- A Perplexity hybrid agentic inference demo runs local data triage on Core Ultra Series 3
- Purpose-built silicon wins put Intel into the merchant custom silicon market
The News: At COMPUTEX 2026 in Taipei, Intel CEO Lip-Bu Tan used his keynote to recast Intel as a systems company built for the agentic AI era. Intel introduced Xeon 6+, its first data center CPU built on the Intel 18A process, with 288 efficiency cores and 576MB of L3 cache. Intel also unveiled an initiative called Rackscale Blueprints, announced rackscale AI infrastructure with SambaNova and Foxconn, showcased a fully disaggregated inference cloud called Vector Core Compute (formed by Vista Equity Partners and Cambium Capital), and ran a live hybrid agentic inference demo with Perplexity CEO Aravind Srinivas. Across client, edge, data center, and emerging intelligence centers, the leadership team maintained that as workloads shift from training to agentic inference, the CPU returns to a position of prominence.
Tan tied the keynote to the rise of inference, agentic, and physical AI, pledging that Intel would deliver “new innovations from the chip to systems level.”
Intel Bets the Data Center on Agentic AI at Computex 2026. Is the CPU Comeback Real?
Analyst Take—Intel Returns to Systems, Not Just Sockets: The loudest signal out of Computex was not a chip. It was Intel reentering the systems business in force. With Rackscale Blueprints, Intel stops selling the part and starts selling the rack, working with Foxconn for integration and SambaNova for acceleration to ship reference designs built on open standards rather than proprietary glue.
The headline number gives the strategy its teeth. A single liquid-cooled Agentic Density CPU Rack with Xeon 6+ can deliver 36,864 cores in 32U at roughly 100 kilowatts, which works out to 128 CPUs per rack. That is roughly double the CPU density of the Arm AGI ORv3 hyperscale racks that reached market this spring, and Intel translated it into the metric that now matters for hyperscalers: up to 150,000 agents per rack. For a company that spent a decade losing the systems narrative to accelerator vendors, this is the most credible systems posture Intel has shown in years.
The substance under the staging is Xeon 6+, being the first data center CPU on Intel 18A. Intel needs 18A to prove out in a high-volume, high-margin product it controls end to end, and a flagship server CPU is exactly that proof point. Futurum has estimated 18A yield stabilization near 65% with further 8% monthly gains disclosed by Lip-Bu Tan. Xeon 6+ shipping in volume is the test of whether that figure holds when the product is the company’s own breadwinner rather than a test chip.
Intel Can Define the CPU:GPU Ratio Through R&D
Kevork Kechichian, EVP of Intel’s Data Center Group, made the most assertive claim of the keynote and refused to hedge it. Training split the data center into two camps, CPU-led enterprise infrastructure on one side and GPU-heavy AI factories on the other, at roughly one CPU per eight GPUs. Kechichian declared that divide over. Agentic AI takes goals rather than prompts and runs an iterative loop of thinking, planning, acting, and reflecting, and that loop lives on the CPU. It uses tools, reads and writes files, checks rules, and spawns concurrent agents, all work that sits in the traditional realm of general-purpose cores. His conclusion was blunt: the CPU orchestrates and coordinates the reasoning process, so the one-to-eight ratio moves much closer to parity, and in agentic workloads, it tips CPU-heavy.
Kechichian backed the stance with an A/B demonstration that his team ran rather than a slide of projections. They sent the same request, write a Python function that calls an OpenAI-compatible chat completions API, to two stacks. Traditional inference ran nearly seven-to-one GPU-heavy. The agentic pipeline flipped it, mapping each stage to the right class of core: orchestration and linting on Xeon 6+ efficiency cores, web fetch and compile on Xeon 6 performance cores, and unit testing back on Xeon 6+ efficiency cores. The on-screen ratio settled near parity and tilted CPU-heavy. This is the core of the R&D argument. Intel has profiled the agentic pipeline stage by stage and engineered a heterogeneous P-core and E-core mix to match it, which is how Kechichian justified the claim that Intel can define where the ratio lands rather than react to it.
Co-Optimization Is the Real Moat, and Perplexity Is the Proof
Intel is now working with the AI engineering community on co-optimization across models and compilers. The Perplexity segment was the proof. Srinivas ran live LBO modeling inside Perplexity Computer, an AI operating system that orchestrates up to 20 models with a model-agnostic agent harness, and the demo kept confidential deal materials on the device. The local model on Core Ultra Series 3 classified what was sensitive, decided what could leave the machine, and spun up cloud research agents for everything else. This is the right answer to NVIDIA’s push to claim the agentic CPU. Intel is responding with IP, performance, and power advantages that scale from the same Core Ultra Series 3 lineage up through Xeon, plus a developer story that competitors building closed stacks cannot easily match. The breadth of model and compiler support will be the moat in this emerging category.
The Rack Becomes a Cloud, and Custom Silicon Becomes the Data Center
The rack does not stay a rack. Vista Equity Partners formed Vector Core Compute with Cambium Capital, and the same Vista-Cambium partnership led SambaNova’s Series E of over $350 million in February, with Intel co-investing. Vista is now re-investing in that portfolio company by building the cloud on SambaNova’s RDUs. The flywheel is clean: Vista funds SambaNova, stands up an inference cloud that buys SambaNova silicon, and routes its own 90-plus portfolio companies (2.5 million enterprise customers, 750 million users) in as anchor demand. Intel sits inside the same loop, holding equity in the accelerator, supplying the Xeon orchestration layer, and contributing the inference software the two companies have been co-developing on Xeon infrastructure. Read this way, an Intel/SambaNova cloud can become a co-financed, co-owned stack where Intel captures the orchestration tier, an equity stake in the accelerator, and the software that binds them.
The custom silicon wins point to the larger build-out. The Google IPU, already deploying, is proof Intel can design and ship purpose-built infrastructure silicon for a hyperscaler at scale, and the Ericsson work extends the same muscle into telecom. That capability does not have to end at offload chips for other companies’ clouds. Intel can leverage it to assemble whole agentic data centers on its own silicon: Intel CPUs for orchestration, Intel GPUs for acceleration, and Intel networking and IPUs for the fabric and infrastructure offload. Once Intel owns the data movement layer inside a hyperscale build, selling the CPU, the GPU, and the network alongside it becomes a far shorter conversation. COMPUTEX framed Intel as a systems integrator. The financing structure and the custom silicon roadmap point at the more ambitious goal, which is to own the agentic data center end to end, from the CPU outward.
What to Watch:
- Xeon 6+ shipping in quantity is the real test of whether the reported 65 percent yield stabilization holds when the product is Intel’s own margin driver
- Where the CPU ratio actually lands in Intel R&D and cloud procurement for agentic data centers
- Disaggregation economics from Vector Core Compute need to hold across many customers and models once Blackwell prefill and SambaNova decode are fully priced in.
- If NVIDIA pushes Vera CPUs to high-volume production, Intel’s x86 install-base advantage gets tested head-on, and the co-optimization moat becomes the thing that has to hold.
See the complete rundown of the chip-to-rackscale announcements on the Intel newsroom.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.
Other Insights From Futurum:
Will Intel Xeon CPUs Increase Google’s CPU:XPU Ratio?
Intel Q1 FY 2026 Earnings Point to Agentic CPU Demand and Foundry Upside
Can Intel Foundry’s Advanced Packaging Bring the Terafab Vision to the Stars?
Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
