As AI-scale workloads push data center CPUs to their limits, chipmakers face a persistent physics problem: extracting more performance from every transistor without blowing through fixed power budgets. Each new process node promises gains, but translating those gains into measured, per-core frequency improvements — the number that determines how fast a single thread of work actually runs — is where the theory meets the silicon.

Intel’s 18A-P process pairs gate-all-around transistors (RibbonFET) with backside power delivery (PowerVia), a combination Intel has measured at roughly 30% higher operating frequency at low voltage on production x86 silicon. It’s the industry’s first transistor architecture shift since FinFET arrived in 2011, and Intel is banking on it to power its next-generation Xeon processor, Diamond Rapids.

In our latest thought leadership brief How Intel 18A-P Transistor Breakthroughs Shape Diamond Rapids CPU Design, completed in partnership with Intel, The Futurum Group examines the silicon-validated data behind Intel’s 18A-P process and explains what it means for Diamond Rapids, Intel’s next-generation Xeon platform built for high-demand IaaS and AI-scale workloads.

In this brief, you will learn:

• How Intel’s pairing of RibbonFET and backside power delivery (GAA-BSPD) converts transistor gains into as much as 30% higher operating frequency at low voltage
• The four design levers Intel is using to extend frequency gains into high-voltage, high-performance designs
• How advanced materials, including subtractive ruthenium interconnect and future z-dimension logic stacking, could extend Intel’s roadmap
• Why Diamond Rapids is positioned to convert Xeon 6+’s efficiency gains into Intel’s leading per-core performance product for the data center

If you are interested in learning more, be sure to download your copy of How Intel 18A-P Transistor Breakthroughs Shape Diamond Rapids CPU Design today.