Analyst(s): Ray Wang
Publication Date: July 1, 2025
Synopsys and Samsung Foundry have expanded their long-standing collaboration to accelerate chip design innovation for advanced edge AI, HPC, and AI applications. The partnership has delivered a successful tape-out of a high-bandwidth memory (HBM3) design using Samsung’s SF2 process and I-CubeS 2.5D packaging, leveraging Synopsys’ 3DIC Compiler to reduce turnaround time by 10x.
What is Covered in this Article:
- Synopsys and Samsung Foundry tape out a customer HBM3 design on SF2 and I-CubeS using Synopsys 3DIC Compiler with 10x faster turnaround time.
- Certified AI-driven digital and analog EDA flows on Samsung’s SF2P process improve PPA and speed system-on-chip (SoC) development.
- Multi-die routing time reduced to 4 hours with improved signal reliability using 3DIC Compiler.
- Synopsys introduces new IP for SF2P and SF4X nodes, including 224G, UCIe, MIPI, and LPDDR6, enabling faster design integration.
The News: Synopsys has expanded its partnership with Samsung Foundry to help push forward edge AI, HPC, and broader AI tech. One major highlight is the successful tape-out of a customer HBM3 design using Samsung’s SF2 (2nm) process and I-CubeS 2.5D packaging. Synopsys’ 3DIC Compiler played a key role, cutting turnaround time by 10x.
As part of the collaboration, Synopsys also got its AI-driven digital and analog EDA flows certified on the SF2P process. The company has rolled out a wide range of high-performance, power-performance, and area (PPA)- optimized IP components that work with Samsung’s advanced nodes. All this makes it easier and faster for customers to bring complex, multi-die SoCs into production with less risk.
Synopsys Strengthens AI and Multi-Die Design Capabilities with Samsung
Analyst Take: This latest move between Synopsys and Samsung Foundry marks progress in making chip design smoother and scaling up advanced semiconductor builds. With Synopsys’ 3DIC Compiler and certified AI-powered flows, customers can develop high-performance, low-power SoCs using Samsung’s cutting-edge tech. This is helping cut down design hurdles and making it easier to plug in pre-integrated IP components across use cases like data centers and edge AI.
Accelerated Multi-Die Design Enablement
Synopsys and Samsung successfully completed a tape-out for a HBM3 (4th generation of HBM)customer design on the SF2 node, using I-CubeS 2.5D packaging and the Synopsys 3DIC Compiler. That tool slashed turnaround time by 10x, with HBM routing wrapped up in just four hours. It also improved worst-case eye opening by 6%, boosting performance and reliability for multi-die connections. This shows how the 3DIC Compiler enables rapid 3D floorplanning, bump and through-silicon via (TSV) planning, and early thermal analysis, as certified by Samsung for X-Cube technology. It lays solid groundwork for scaling complex multi-die systems using Samsung’s advanced packaging tech.
Certified EDA Flows Streamline AI Design
Synopsys’ AI-based digital and analog design flows are now certified for Samsung’s SF2P process, which makes it easier for chipmakers to get better PPA and streamline development. These flows support hypercell enablement, helping improve design density by using standard cell areas more effectively. This certification means customers can plug these tools into their workflows without extra steps. That translates into quicker, better-quality designs ready for Samsung’s under-2nm tech. The increasing AI-driven EDA software, as pushed by Synopsys and other EDA players in recent years, should be a key trend to watch in the semiconductor industry, which could lead to a more cost-effective, precise, and efficient chipmaking process.
IP Availability Eases Time-to-Market Pressure
Synopsys now offers a wide range of IP blocks, like 224G, UCIe, MIPI, and LPDDR6, tailored for Samsung’s SF2P and SF4X processes. The company also included PCIe 7.0, USB4, memory blocks, logic libraries, GPIOs, and Silicon Lifecycle Management (SLM) IP, all tuned for PPA and latency across Samsung’s advanced process nodes. This IP library helps reduce risk and shortens development time with pre-verified building blocks. Access to this kind of high-quality IP helps teams hit deadlines faster and stand out in fast-moving markets.
Continued Momentum in Design Technology Co-Optimization
Synopsys and Samsung are still working together on design technology co-optimization (DTCO), using Synopsys’ ASO.ai and schematic migration flows to move analog IP from SF4 to SF2. This makes it easier to shift designs over without starting from scratch. The DTCO work focuses on pulling improved PPA performance from Samsung’s SF2 and SF2P nodes. By making combining old and new IP easier, the companies are helping designers save time and scale up performance. These DTCO efforts reinforce Synopsys and Samsung’s goal of accelerating high-performance design enablement across advanced nodes while supporting efficient IP reuse.
What to Watch:
- Adoption and outcome of certified AI-driven EDA flows and IP portfolios by additional customers on Samsung’s SF2 and SF2P process nodes.
- Expansion of Synopsys 3DIC Compiler and schematic migration capabilities to broader design ecosystems within multi-die environments.
- Competitive pressure on other EDA vendors to match Synopsys’ level of integration and certification with leading foundry partners.
- Ecosystem impact as customers leverage Synopsys-Samsung collaboration to shorten time-to-market for AI, HPC, and edge designs.
See the complete press release on Synopsys and Samsung’s advanced design collaboration on the Synopsys website.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.
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Author Information
Ray Wang is the Research Director for Semiconductors, Supply Chain, and Emerging Technology at Futurum. His coverage focuses on the global semiconductor industry and frontier technologies. He also advises clients on global compute distribution, deployment, and supply chain. In addition to his main coverage and expertise, Wang also specializes in global technology policy, supply chain dynamics, and U.S.-China relations.
He has been quoted or interviewed regularly by leading media outlets across the globe, including CNBC, CNN, MarketWatch, Nikkei Asia, South China Morning Post, Business Insider, Science, Al Jazeera, Fast Company, and TaiwanPlus.
Prior to joining Futurum, Wang worked as an independent semiconductor and technology analyst, advising technology firms and institutional investors on industry development, regulations, and geopolitics. He also held positions at leading consulting firms and think tanks in Washington, D.C., including DGA–Albright Stonebridge Group, the Center for Strategic and International Studies (CSIS), and the Carnegie Endowment for International Peace.
