Analyst(s): Brendan Burke
Publication Date: July 24, 2026
At Advancing AI 2026, AMD launched the Helios rackscale solution and the Instinct MI400 Series GPUs, claiming 15% more FP4 compute, 50% more HBM capacity, and 50% more scale-out bandwidth than NVIDIA’s Vera Rubin NVL72. The comparison marks the first GPU generation in which AMD enters at spec parity with NVIDIA’s flagship rack rather than a step behind it. The durable advantage, however, remains flexibility and support for open standards rather than any single benchmark.
What Is Covered in This Article:
- AMD launched the Helios rackscale solution at Advancing AI 2026, integrating 72 Instinct MI455X GPUs, 6th Gen EPYC CPUs, Pensando Vulcano 800 AI NICs, and ROCm software to deliver 2.9 exaflops of peak FP4 compute, 31 TB of HBM4, and 1.7 PB/s of memory bandwidth per rack.
- AMD launched the Instinct MI400 Series GPUs, pairing the MI455X for frontier AI and AI factory deployments with the MI430X for sovereign AI and HPC, which delivers up to 288 TFLOPS of hardware-based FP64 performance.
- AMD-modeled comparisons favor Helios over NVIDIA’s Vera Rubin NVL72: 15% more peak FP4 compute, 50% more HBM capacity, 6% more HBM bandwidth, 50% more scale-out bandwidth, double-digit gains in tokens per second per GPU across interactivity levels, and up to 30% more tokens per dollar.
- MI455X architectural disclosures include a chiplet architecture that partitions compute, memory, cache, and I/O across specialized dies; transcendental engines optimized for attention; dedicated DMA engines; and CDNA 5 microarchitecture that parallels NVIDIA’s execution model with ROCm support.
- AMD committed to an annual roadmap cadence, with MI500 bringing next-generation HBM, a larger scale-up domain, and copper and optical interconnect, and MI600 already in development.
The News: At Advancing AI 2026, AMD launched the Helios rack-scale AI infrastructure platform. Each Helios rack integrates 18 open-rack, wide-aligned compute trays of four Instinct MI455X GPUs each with 6th Gen AMD EPYC server CPUs, AMD Pensando DPUs, and AMD ROCm software. A single rack delivers up to 2.9 exaflops of peak FP4 and 1.4 exaflops of peak FP8 compute, 31 TB of HBM4 memory, and 1.7 PB/s of memory bandwidth. AMD states that Helios delivers 15% more peak FP4 performance, 50% more HBM capacity, 6% more HBM bandwidth, 50% more scale-out bandwidth, and up to 30% more tokens per dollar than the leading competitive solution, the NVIDIA Vera Rubin NVL72, based on AMD Performance Labs calculations and modeling.
AMD also launched the Instinct MI400 Series GPUs, the portfolio underpinning Helios. The family includes the MI455X for frontier AI and AI factory deployments and the MI430X for sovereign AI and HPC, the latter delivering up to 288 TFLOPS of hardware-based FP64 performance for scientific computing. The portfolio combines HBM4 memory, advanced security features including secure boot and encrypted GPU-to-GPU links, and the open ROCm software stack.
AMD Helios Reaches Parity with Vera Rubin NVL72: Can Open Standards Outflank NVIDIA?
Analyst Take: AMD Helios arrives as the company’s first rack-scale platform engineered to meet NVIDIA’s flagship on its own terms. AMD claims Helios delivers 15% more peak FP4 compute with 2.9 exaflops, 50% more memory with 31 TB of HBM4, and 50% more scale-out bandwidth at 43 TB/s than the NVIDIA Vera Rubin NVL72. While this is task-specific modeling, AMD is no longer positioning Instinct as the value alternative, running a generation behind. The durable advantage, however, is not any single spec. It is flexibility and support for open standards — UALink over Ethernet for scale-up, Ultra Ethernet Consortium alignment for scale-out, and ROCm’s open software foundation — that let customers assemble AI infrastructure without committing to a single vendor’s fabric roadmap.
The stakes are expanding faster than the silicon. Futurum projects the data center chip market will reach $1.2 trillion by 2030, with GPUs holding roughly half of that total at $604.5 billion on a 30.8% CAGR. AMD enters this cycle with committed demand that earlier Instinct generations lacked from customers, including Anthropic, OpenAI, Meta, and Microsoft. The question is no longer whether AMD can win frontier AI deployments. It is whether Helios converts spec sheet leadership into sustained share while NVIDIA ships Vera Rubin NVL72 into the same window.
AMD Helios Outspecs Vera Rubin NVL72 on Paper, but Openness Is the Durable Advantage
The memory advantage is the most defensible of AMD’s claims. Helios carries 31 TB of HBM4 per rack against the Vera Rubin NVL72’s published 20.7 TB, and 1.7 PB/s of aggregate bandwidth against 1.6 PB/s. For large-model inference, where KV cache capacity governs batch size and context length, a 50% capacity advantage translates directly into serving economics. On the fabric side, Helios pairs 43 TB/s of scale-out bandwidth — 50% more than the NVIDIA rack — with roughly 260 TB/s of scale-up bandwidth that matches the NVL72’s NVLink 6 fabric. AMD’s modeling shows double-digit gains in tokens per second per GPU compared to Vera Rubin NVL72 across low-, medium-, and high-interactivity operating points, measured on the Kimi K2 Thinking workload with a 32K input and 8K output sequence profile, aggregating to a claimed 30% advantage in tokens per dollar.
It is unlikely that customers will experience these precise advantages. The 15% FP4 advantage compares AMD’s peak datatypes against NVIDIA’s published NVFP4 dense specifications, while NVIDIA markets the NVL72 at 3.6 exaflops of sparse NVFP4 inference. The two figures describe different arithmetic, and buyers will see vendors argue past each other on this point for the next year. Modeled throughput is a thesis rather than a procurement mandate. Both racks will reach production in the second half of 2026, and neither has public, third-party production benchmarks. AMD may not win every inference benchmark, yet they have provided a competitive product that leading frontier AI customers can adapt to their needs.
What AMD can defend regardless of benchmark outcomes is architecture governance. Helios is built on UALink over Ethernet for scale-up and standards-based Ethernet aligned with the Ultra Ethernet Consortium for scale-out, meaning hyperscalers can substitute switches, NICs, and eventually accelerators without abandoning the rack design. NVIDIA’s NVLink 6 delivers formidable fabric bandwidth but binds the customer to NVIDIA’s interconnect roadmap. For buyers planning gigawatt-scale clusters across multiple silicon generations, that flexibility compounds in a way single-generation spec deltas do not.
Chiplet Partitioning and Transcendental Math Throughput Close the Per-GPU Gap
AMD asserts that process and architecture innovations enable the MI455X to deliver performance comparable to the Vera Rubin GPU. The chiplet architecture partitions compute, memory, cache, and I/O across specialized dies, allowing AMD to optimize each function independently rather than forcing every subsystem onto one process node and one reticle budget — the same disaggregation logic that carried EPYC past monolithic server CPUs.
The attention pipeline receives the most pointed optimization: the MI455X adds transcendental math engines tuned for attention workloads, including a new hyperbolic tangent transcendental operation, doubles the throughput of all transcendental operations carried over from the MI355X, and increases compute per clock cycle. Softmax and activation functions sit on the critical path of every attention block, so transcendental throughput converts directly into decode performance in exactly the interactivity-sensitive serving scenarios AMD is benchmarking against NVIDIA.
A dedicated DMA engine moves data independently of work groups, overlapping data movement with computation instead of stalling compute units on memory traffic. The implication is that AMD is engineering for the inference-dominated era rather than retrofitting a training part, consistent with the industry’s broader pivot from training-centric to inference-dominated infrastructure.
An Annual Cadence Through MI600 Raises the Cost of Keeping Pace
AMD paired the launch with roadmap commitments that extend the argument beyond a single rack. In event commentary, AMD executives said the MI500 brings the next generation of HBM to bear, a larger scale-up domain, and both copper and optical interconnect to push performance further, with the MI600 already in development on the same annual cadence. The MI430X extends the portfolio in the other direction, into sovereign AI and leadership-class HPC, where 288 TFLOPS of hardware-based FP64 addresses the numerical-accuracy requirements that FP4-optimized frontier silicon abandons — a dual-track portfolio strategy no other merchant silicon vendor currently matches.
The risk is symmetrical. NVIDIA is executing the same annual cadence, with Rubin Ultra configurations already disclosed for 2027, so any Helios advantage must be re-won every twelve months. An annual cadence also concentrates supply-chain exposure: both vendors will compete for the same HBM allocation, and optical interconnect at MI500 scale introduces manufacturing complexity AMD has not shipped in volume before. Spec leadership in July 2026 is an entry ticket to that race, not a victory in it.
What to Watch:
- Third-party benchmarks and early operator data from the Microsoft Helios ramp in H2 2026 will determine whether the double-digit throughput advantage survives contact with production workloads.
- NVIDIA’s Rubin Ultra roadmap for 2027 could compress any Helios advantage to a two- to three-quarter window.
- UALink alignment is only an advantage if the ecosystem ships — watch for third-party switch and server vendors building to the Helios rack specification.
- ROCm releases that tune kernels and serving frameworks to exploit thread-block clusters and the tensor data mover for day 0 support of frontier models.
- Memory supply will govern how fast AMD’s committed gigawatts materialize.
See the complete announcement of the Helios rackscale solution and Instinct MI400 Series in the AMD newsroom.
Disclosure: Futurum is a research and advisory firm that engages or has engaged in research, analysis, and advisory services with many technology companies, including those mentioned in this article. The author does not hold any equity positions with any company mentioned in this article.
Analysis and opinions expressed herein are specific to the analyst individually and data and other information that might have been provided for validation, not those of Futurum as a whole.
Other Insights From Futurum:
Azure’s AMD Partnership Expands: Is Reinforcement Learning the Hardware Bottleneck?
Can AMD and Rackspace Scale Sovereign AI Inference?
Can AMD EPYC Extend Its Lead Over Vera and Xeon in the Agentic Data Center?
Author Information
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.
